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dc.contributor.author吳介琮en_US
dc.contributor.authorWU JIEH-TSORNGen_US
dc.date.accessioned2014-12-13T10:51:51Z-
dc.date.available2014-12-13T10:51:51Z-
dc.date.issued2007en_US
dc.identifier.govdocNSC96-2220-E009-036zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/102933-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=1464419&docId=262492en_US
dc.description.abstract<![CDATA[ 本計畫是「助�器晶片�系統�整�型計劃的一個�計畫。目的是設計�實�此系統所需�的低功率混�訊號�介�電路，並且將與其他數�電路整�於�一晶片上。本計劃將開發（1）微機電麥克風�置放大器與類比數�轉�器；（2）微機電喇�驅動電路；（3）電�控制電路。在麥克風接收端，訊號的頻寬有 20 kHz，而訊號的動態範�（Dynamic Range）�高� 100 dB。雖然傳統的 Delta-Sigma ADC 有足夠的動態範�，但也比較耗電。本�計劃將研究更有效率的類比數�轉�方法。在喇�端的驅動電路將會是整個助�器系統最耗電的部份。本�計劃將��特殊設計的微機電喇�以高效率的方�驅動。所有電路將加入自動調整功能，它能根據製程�電壓�溫度（Process, Voltage, Temperature, 簡稱 PVT）的變化自動調整功率消耗，因而能在所需的效能�求下有最低的功率消耗。本計劃的電路設計將追求最佳功率效益。 本計畫的所有電路，除了微機電麥克風�喇�外，最後將整�於 90 nm 的 CMOS 單晶片中。以 1 V 電池�作，類比電路的功率消耗�得超� 500 uW。�外，所發展的電路都會以「晶片效能指標�（Chip Performance Index, CPI）來和功能類似的電路相比較。而本計畫的目標就是追求最佳的 CPI。#2; ]]>zh_TW
dc.description.abstract<![CDATA[ This project is one of the sub-projects of the 「Hearing Aid SoC and System� project. The objective is to design and realize the essential low-power mixed-signal interface circuits, and then integrate those circuits with other digital circuits on the same chip. This project will develop (1) a MEMS microphone preamplifier followed by an analog-to-digital converter; (2) a MEMS speaker driver; and (3) supply control circuits. At the microphone end, the required signal bandwidth is 20 kHz and the dynamic range is as high as 100 dB. Although the conventional Delta-Sigma ADC can achieve the required dynamic range, it also demands premium power dissipation. We will develop a more power-efficient A/D technique. At the speaker end, the driver will consume most of the energy resource. We will work with the MEMS team to improve the power efficiency of the speaker system. All circuits will contain automatic adjustment mechanism in response to process, voltage, and temperature (PVT) variation. The goal is to achieve minimum power consumption while meeting the performance requirements. In this project, all circuit design will pursue the optimal power efficiency. Except the MEMS microphone and speaker, all circuits will be integrated on a signal chip fabricated in a 90 nm CMOS technology. Operating under a 1 V battery supply, the total power consumption for the analog circuits will be less than 500 uW. Circuits designed in this project will be compared with known designs of similar functions, using the Chip Performance Index (CPI). The goal of this project is to achieve the best CPI. ]]>en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.subject低功率類比電路zh_TW
dc.subject混合訊號式積體電路zh_TW
dc.subject助聽器zh_TW
dc.subjectLow-Power Analog Circuitsen_US
dc.subjectMixed-Signal Integrated Circuitsen_US
dc.subjectHearing Aids.en_US
dc.title助聽器晶片及系統---子計畫六：助聽器類比介面電路(I)zh_TW
dc.titleAnalog Interface Circuits for Hearing Aid SoC(I)en_US
dc.typePlanen_US
dc.contributor.department國立交通大學電子工程學系及電子研究所zh_TW
顯示於類別：研究計畫


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