低壓降線性穩壓電路的靜電放電防護應用

Abstract

本篇論文詳細討論了利用低壓降線性穩壓器，來實現靜電放電防護應用，文章內容主要可以分成二個部分。第一部分是探討低壓降線性穩壓器。隨著可攜式電子產品的快速發展，例如：手機、數位照相機等等；電源管理已經變得越來越重要與關鍵，並且朝著減少功率消耗發展。低壓降穩壓器大量的用在電源管理上，因為相較於切換式的穩壓器有著較好的暫態響應、較小的雜訊與較少的外接元件。 穩定度一直是在設計低壓降線性穩壓器的過程中一個重要的議題。在傳統的電路架構中，負載電流大小以及輸出電容值為兩項主要影響穩定度的因素。因此，到目前為止已有許多補償的方法被提出來改善整體的效能。就應用的方面來說大致分為輸出電容外接和內建兩類，利用電容外接的方式可增加輸出電容的容值並產生一個主極點維持穩定，主要應用在系統較大對於面積較不注重的產品如電視。另一類的低壓降線性穩壓器的輸出電容靠著米勒效應使得電容值小且可整合在晶片當中，省下不少面積因此適合應用在可攜式電子產品裡作為穩定的直流電壓源。 第二部分探討靜電放電防護應用。功率電晶體雖然被設計應用於高電壓、大電流的偏壓條件，但對於動輒上千伏特的靜電放電電壓、數安培的靜電放電電流而言，功率電晶體仍嫌脆弱，所以為了確保功率電晶體等高功率元件的可靠度，靜電放電保護電路設計是當務之急。 當積體電路製成的精密度，越來越細緻，積體電路的可靠性工程，一直有著非常重要的地位，在設計、製程、技術的改善，均可提高積體電路的可靠度，在良率提升之後，還有其他影響可靠性工程的因素，ESD的破壞是其中之一項，而遭ESD的破壞是可避免的，學術上已有許多的ESD保護電路的產生。本論文將以保護電路的元件做ESD電擊測試，分析其抗ESD能力。

The thesis proposes a low-dropout (LDO) regulator with ESD Impacts. Thus, the content of this thesis contains two parts. The first part discusses the design of a low-dropout regulator. With the exponentially increasing of portable battery-powered electronic equipments, such as mobile phones, digital cameras and so on, power management has becoming more and more important and popular. The design of low dropout regulators is widely used in power management since it has a better load transient response, less output noise, and few off-chip components compared to the design of switch-mode regulators. Stability is an important issue in the design of LDO linear regulators. In the conventional architecture, the key factors affecting the system stability are the wide load current range and the value of the output capacitor. Therefore, there exist many proposed compensation techniques to stabilize and improve the whole system. According to the type of output capacitor, LDO regulators can be simply classified into two groups: LDOs with off-chip or on-chip output capacitor. These LDO linear regulators with off-chip capacitor need a large capacitance at output node to generate a dominant pole at low frequency to achieve the stability. They are mostly used for supplying the system with the characteristic of low quiescent current at light loads owing to the current efficient buffer used in the LDOs. The other LDO regulators use an on-chip small output capacitor based on the Miller-compensated technique. Thus, the capacitor can be integrated into the chip, which has the advantage of the saving the footprint area. This type of capacitor-free LDOs is well suited as a stable dc voltage supply for portable electronic devices. The second part of this thesis discusses how ESD impacts the low-dropout regulators. In some situation, the latent damage of electrostatic discharge in a power MOSFET can't easily find out immediately. Eventually, in order to make sure a good reliability and long lifetime of power MOSFETs, the ESD protection circuit design is needed to prevent ESD damages in a power MOSFET design. This thesis provides the reliability engineers of integrated circuit a most important concept of ESD design of power IC. The improvement of the ESD will enhance the reliability of integrated circuit in power IC designs.