SONOS記憶體因寫入電子之隨機特性造成臨界電壓擾動之模擬分析

Abstract

SONOS記憶體是以氮化矽(Si3N4)作為電荷陷捕層(Charge Trapping Layer)來取代傳統以多晶矽來儲存電荷的浮閘極元件。由於氮化矽是以單顆離散的陷捕(Trap)來儲存電荷，因此會造成非均勻的通道位能，進而導致臨界電壓受到儲存電荷排列方式的影響。換而言之，當通道中電子導通的路徑不同時,便會造成臨界電壓擾動的現象。在此篇論文中，採用三維飄移擴散模型(Drift-Diffusion) ，並以ISE為工具對SONOS元件中因儲存於氮化矽內的寫入電子隨機排列所造成臨界電壓擾動的現象進行研究。 首先模擬在不同的元件參數下(通道長度、通道寬度、寫入電壓窗(Program Window)以及頂層與底層的氧化層厚度)對於臨界電壓擾動的影響。在每項參數中，均以一百個具有不同排列之寫入電子的元件來進行統計VT的變化量,以對每項參數進行分析。 模擬的結果顯示，當元件微縮以及寫入電子的數量變多時會讓VT的分佈曲線變寬，此外，底層氧化層的厚度變薄會讓VT的擾動變的更嚴重，其原因在論文中有詳細的論述。根據模擬結果，利用high-k材料來取代頂層氧化層能有效的改善此現象。最後為了更接近記憶體元件實際的情形，將隨機摻雜的因素也加入模擬中，可以預見的，這項因素的加入會讓VT的擾動變的更加嚴重。雖然在通道加入低摻雜的磊晶層(epi-taxial layer)可抑制隨機摻雜造成的問題，但仍無法有效降低寫入狀態的VT擾動，由此可知隨機寫入電子是造成VT擾動最主要的因素。

Instead of using a conducting poly layer as a storage node in a conventional floating gate device, a charge trap cell utilizes discrete trapping centers of an appropriate dielectric film to achieve a similar memory function. In such structure, the channel potential becomes inhomogeneous due to the discreteness of the storage charges and thus the threshold voltage (VT) will strongly depend on how an inversion percolation path from source to drain is formed in the channel. In this work, SONOS devices with randomly distributed storage charges in a nitride layer are used and the induced VT fluctuations are then emulated by using a three-dimensional drift-diffusion simulator (ISE). In the beginning, the effects of various parameters including channel length, channel width, program window, and both top and bottom oxide thicknesses on the VT fluctuation are studied. For each case, samples of 100 microscopically different programmed cells are used. The statistics variation of VT are then collected and analyzed with respect to each variable. Basically, more programmed charges or the shrinkage of device dimensions will worsen the VT distribution. Besides, the bottom oxide shows more pronounced effect than the top oxide and reasons will be given in this thesis. Finally, to further approach the real situations of memory cells, the effect of random charges with random dopants are also investigated. As expected, the fluctuation of cells gets even worse. Adopting an epi-taxial layer with a lightly doped concentration on the Si surface is useful for suppressing the random dopant effect. But the program state threshold voltage fluctuations can not be improved significantly. Thus, the random charge effect is the main source induced the dispersion of VT.