完整後設資料紀錄
DC 欄位語言
dc.contributor.author謝易叡en_US
dc.contributor.authorE Ray Hsiehen_US
dc.contributor.author莊紹勳en_US
dc.contributor.authorSteve S. Chungen_US
dc.date.accessioned2014-12-12T01:13:41Z-
dc.date.available2014-12-12T01:13:41Z-
dc.date.issued2007en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009511539en_US
dc.identifier.urihttp://hdl.handle.net/11536/38078-
dc.description.abstract本論文首次提出一種改良的新式直流電流-電壓量測法-βDC-IV(Boosted DC-IV),此方法可成功地應用在EOT小於或等於13 A0以下的CMOS元件。另一方面,我們也首次完成氧化層之介面缺陷之橫向分佈,此法被成功地應用於偵測從通道至閘極邊緣的介面缺陷之可靠度研究。 本論文中,吾人利用上述所提及的量測方法來探討各種應變矽元件技術之可靠性分析, 並且獲致以下兩點主要的結論: (1) 對於應變矽nMOSFET元件而言,介電層覆蓋式(CESL)元件擁有較好的可靠度以及性能表現。應變絕緣層上矽(Strained Silicon-on-insulator, SSOI)元件擁有較好的熱載子抵抗能力,但其通道介面品質有待提升。矽碳化物(SiC)元件的效能提昇是明顯的,但是其汲極(drain)之接面品質必須改善。SiGe元件擁有很好的性能提昇表現,但是其Ge-out diffusion的問題卻是必須克服的。 (2) 對於應變矽pMOSFET元件而言,SiGe在S/D元件擁有較好的可靠度以及性能提昇表現。而SiGe在channel元件有較差的負偏壓不穩性(Negative Bias Temperature Instability, NBTI)表現。 隨著CMOS元件技術持續地演進,應變矽技術將越形重要,本論文對於如何利用應變矽技術設計一兼具可靠性與性能的優越CMOS元件提供重要設計準則。zh_TW
dc.description.abstractFor the first time, an improved DC-IV measurement has been developed for the reliability study of devices with EOT down to 13A0, and also a new interface-trap lateral-profiling technique has been built. It can be used to accurately profile the interface traps distributions along the device channel. By performing the above characterization and measurements, the reliabilities of the strain CMOS have been studied, from which two conclusions have been provided: (1) For strained nMOSFETs, nitride-capped devices are appreciated in terms of reliability and performance. SSOI devices have good hot-carrier immunity and performance, but its channel interface quality has to be improved. The performance of SiC devices is good, but the junction quality is worse. The SiGe on substrate devices exhibit very good performance, but the Ge-out diffusion effect is so serious that these devices are unreliable. (2) For strained pMOSFETs, SiGe on S/D devices will be appreciated in terms of performance and reliability. Also, SiGe on channel devices have worse NBTI property. As a consequence, from the future perspective, it is necessary to make a trade-off and to find the best strategy to improve the performance and, meanwhile, keep reliability. All the results in this thesis will be valuable to provide a design guideline for designing advanced CMOS devices with both good performance and reliability.en_US
dc.language.isoen_USen_US
dc.subject金氧半互補式電晶體zh_TW
dc.subject應變矽zh_TW
dc.subject可靠度zh_TW
dc.subject閘控二極體法zh_TW
dc.subject直流電壓電流法zh_TW
dc.subject電荷幫浦法zh_TW
dc.subjectCMOSen_US
dc.subjectstrained siliconen_US
dc.subjectreliabilityen_US
dc.subjectgated diode measurementen_US
dc.subjectDC-IV measurementen_US
dc.subjectcharge pumping measurementen_US
dc.title一種改良的介面缺陷之橫向剖面分析應用於奈米級應變矽CMOS元件之可靠度探討zh_TW
dc.titleAn improved Interface Traps Profiling on the Study of Reliability in Strained CMOS Devicesen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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