使用金屬閘極的鉿類介電層結構之研究

Abstract

即便是在Intel公司已經引入鉿類高介電係數介電材料製造他們產品的現在，人們仍然尚未清楚地瞭解這個新材料的各種特性。直接將高介電係數材料沉積在矽基板上會導致在兩者界面生成預料之外的中間層，其不好的界面特性將造成載子遷移率的劣化；為了得到較佳的界面特性，在沉積高介電係數材料之前先對矽基板進行某些前處理，藉以形成品質較為良好的中間層是必要的作法。另一方面，在沉積高介電係數材料之後使用一些電機製程方法以改善高介電係數薄膜的品質和提升結構的效能也是近來被廣泛研究的一種新想法；這些電機製程方法同時也可減小前處理形成的中間層厚度，並可抑制閘極漏電流。

本篇研究著重在使用金屬閘極的鉿類介電層結構之特性分析，也同樣重視結構對高溫熱製程的容忍度表現。介電層沉積前的表面處理搭配介電層沉積後的電機製程可以降低使用金屬閘極的鉿類介電層結構它的介電層等效氧化厚度，因而結構可呈現出較高的電容值，此外，還兼具較小的閘極漏電流。

Until today, even if Intel Corporation already manufactured their product with hafnium-based high dielectric constant (high-k) dielectric, the characteristics of it are not totally understood. The unexpected interlayer results from direct deposited high-k gate dielectric film on underlying silicon substrate causes deterioration of carrier mobility due to the inferior interface. For better interface and adhesion consideration, insertion of interlayer between high-k dielectric and silicon substrate by introducing pre-gate dielectric deposition treatment is an inevitable tendency. Moreover, post-gate dielectric deposition engineering is being enthusiastically investigated as a novel method improving gate dielectric quality and aspiration for better performance, in further, reducing interfacial layer thickness and gate leakage current. Incorporate with thermal tolerance consideration, this investigation focuses on the characterization of metal gate with alternative gate dielectric concurrently. The utility of pre-gate dielectric deposition treatment with added post-gate dielectric deposition engineering is demonstrated. High capacitance or low equivalent oxide thickness thus can be achieved simultaneously with low gate current.