高介電係數介電質與金屬閘極製程技術之研究與應用

Abstract

隨著互補式金氧半電晶體(CMOS)元件尺寸持續微縮，傳統的絕緣層-二氧化矽(SiO2)將遭遇漏電流過大的物理限制。另外，傳統的多晶矽閘極也將遭遇諸多挑戰-多晶矽空乏、硼穿透及高電阻係數。因此，新的絕緣層及閘極材料將是往後幾年超大型積體電路(VLSI)發展極需解決的問題。近年來，高介電係數介電層與金屬閘極的技術發展，已成為半導體產業最重要的研究之一。在本論文中，吾人將探討數種高介電係數介電層與金屬閘極的研究與應用。 首先，我們將探討高介電係數氮氧化矽鉿(HfSiON)介電層，分別選用矽化鉿(HfSix)與矽化銥(IrxSi)所形成的全金屬矽化閘極(FUSI)來當n-型與p-型金氧半場效電晶體的閘極。而氮氧化矽鉿雖然比氧化鉿有較低的介電係數，但卻有較佳的熱穩定性。另外，使用矽化鉿與矽化銥全金屬矽化閘極比純金屬閘極有更好的熱穩定性，且可有效降低費米栓(Fermi-level pinning)效應所造成的有效功函數偏移現象。結果顯示，結合氧化矽鉿與矽化鉿與矽化銥全金屬矽化閘極，是實現雙金屬閘極互補式金氧半電晶體很好的選擇之一。 其次，我們將探討另一種高介電係數介電層氮氧化鑭鉿(HfLaON)，結合金屬氮化物閘極氮化鉭(TaN)應用於n-型金氧半場效電晶體。氮氧化鑭鉿與氮氧化矽鉿同樣具有良好的高溫熱穩定性，但氮氧化鑭鉿卻有比氮氧化矽鉿還要高的介電係數的優點。此外，氮化鉭閘極具有良好的高溫熱穩定性，且結合氮氧化鑭鉿介電層後，其有效功函數將可調變到適用於n-型金氧半場效電晶體的應用。 最後，我們將高介電係數氧化鑭鋁(LaAlO3)應用於低溫複晶矽薄膜電晶體(Low Temperature poly-Si TFTs)並結合低功函數鐿(Yb)金屬閘極，可以有效降低有效氧化層厚度(EOT)來達成提升電流密度及降低臨界電壓，進而得到大的驅動電流元件特性。此良好的元件特性並無經過氫化及特殊再結晶製程，且將可應用於未來的面板系統(SOP)上。

To continue down-scaling CMOS technology, traditional insulator layer - SiO2 will face the physical limitation - large gate leakage current. In addition, traditional poly-Si gate encounters several inherent limitations, such as poly-Si depletion, boron penetration, and high resistivity. Therefore, new insulator and gate material technologies will become urgent for very large scale integration (VLSI) technology in the future years. Recently, metal-gate/high-k process technologies become one of the most important researches in the semiconductor industry. In this dissertation, we will investigate the application of several high-k dielectric and metal gate process technologies. First of all, we will study the application of HfSiON dielectric with HfSix and IrxSi full silicidation (FUSI) metal gates in n-MOSFETs and p-MOSFETs, respectively. Although HfSiON has smaller dielectric constant than HfO2, it has better thermal stability. Besides, using HfSix and IrxSi FUSI metal gates can obtain better thermal stability than using pure metal gates, and also can reduce the effective work function shifts due to Fermi-level pinning effect. These results indicate that integrating HfSiON with HfSix and IrxSi FUSI metal gates can achieve dual metal gates development in CMOS technology. Next, we will study another high-k dielectric HfLaON with metal nitride TaN gate in n-MOS application. HfLaON has good thermal stability as HfSiON, but it has the advantage of higher k value. Moreover, TaN also has similarly good thermal stability. Integrating HfLaON with TaN gate will provide the appropriate effective work function in n-MOS application. Finally, the application of high-□ LaAlO3 dielectric into low-temperature poly-Si thin-film transistors (TFTs) combining with low work function Yb metal gates was investigated. Good TFT performance was achieved - such as a high drive current and low threshold voltage due to the down-scaling effective oxide thickness (EOT) provided by the high-k dielectric. In addition, the good performance was achieved without hydrogen passivation or special crystallization steps. These results suggest that the Yb/LaAlO3 TFTs can meet the device requirements for system-on-panel (SOP) applications.