標題: 金屬閘極及高介電係數介電質材料在奈米電子元件的應用
The Applications of Novel Metal Gate and High-K Dielectrics for Nano Electronic Devices
作者: 荊鳳德
CHIN ALBERT
國立交通大學電子工程學系及電子研究所
關鍵字: 金屬閘極;高介電係數;互補式金氧半;Metal-gate;High-?dielectric;CMOS
公開日期: 2008
摘要: 缺乏適當的金屬功函數當作閘極電極(Metal gate)和費米能階拴鎖效應 (Fermi-level pinning)是金屬與高介電係數介電質材料應用在矽奈米-互補式金 氧半場效電晶體元件上兩個最主要的問題。尤其,製作p 型金屬閘極/高介電係 數介電質金氧半場效電晶體更是特別的困難。其原因為在所有元素週期表中,只 有銥金屬(Ir:功函數為5.27eV)和鉑(Pt:功函數為5.65eV)之功函數值是高 於被要求的5.2eV。雖然飛思卡爾公司(Freescale Semiconductor)已經發表了使 用碳化鉭材料當作金屬閘極電極並獲得良好的n 型金氧半場效電晶體特性,但是 開發其他具低功函數的金屬或金屬氮化物(MN)材料仍然是需要的。這是因為 金屬與氮(M-N)的鍵結能普遍比金屬碳化物中金屬和碳(M-C)的鍵結能高而 具有較穩定的特性。 本計畫主持人-荊鳳德教授近年來在雙功函數金屬閘極互補式金氧半電晶體 之研究(發表於2003 年IEDM)與高功函數氧化銥閘極在互補式金氧半電晶體 之研究(分別發表於2004 年IEDM 及2005 年VLSI)已有相當的成果(附件一)。 因此,我們希望能開發出適用的金屬閘極材料並獲得適合應用於n 型金屬閘極/ 高介電係數介電質金氧半電晶體場效上的有效功函數:4.2 eV 以及適合應用於p型金屬閘極/高介電係數介電質金氧半場效電晶體上的有效功函數:4.9eV~5.1 eV。 由於計畫主持人-荊教授近幾年來與加拿大國家研究中心的S.P. McAlister 教授在奈米電子元件方面的研究合作已有相當的成果(已發表數 十篇論文在國際知名期刊和會議,附件二),所以,在此研究計畫中,我們 將繼續與加拿大國家研究中心合作。此外,我們也將與新加坡國立大學- 國家奈米元件實驗室(SNDL)合作。新加坡國立大學-國家奈米元件實 驗室是目前在固態電子元件領域最傑出的學術研究單位之一(附件三), 基於雙方友好的關係與之前合作的前例,相信會有很大的收穫與進展。 最後,此計畫也將由國立交通大學張俊彥校長及電資學院吳重雨院長所共同 協助指導與背書。
The lacking of proper work-function metal electrode and Fermi-level pinning are the major challenges for metal-gate/high-豈CMOS. This is especially difficult for pMOS since only the Ir (5.27eV) and Pt (5.65eV) in the Periodic Table are above the required 5.2eV. For nMOS good device using TaC gate is reported by FREESCALE, but it is still desirable to develop the low work-function metal-nitride (MN). This is because the M-N band is generally higher than M-C (metal-carbide). In addition, it is possible to find as stable and low work-function MN as TaC. For p-MOS, the IrO2 has excellent work-function of 5.1eV but the decomposition of IrO2 is will known and also reported by FREESCALE. In addition, the developed dual work-function gates on high-k dielectric should have process compatible with current VLSI process line, which should be stable during process. It is important to note that the above results have never been achieved yet. It is important to note that the TaC is still questionable due to the fundamental understanding of low band strength. The poor band strength is also the problem of the new TaYbN reported in Symp. on VLSI 2005, which will never work from both our experiments and theoretical understanding. Based on our previous works in Full Silicidation (FUSI) dual work-function metal gates (IEDM 2003) and the high work-function IrO2 gate (IEDM 2004, Symp. on VLSI 2005), we hope we can develop dual work function gates with effective work-function (訌m,eff) ~4.2 eV for nMOS and ~4.9-5.1 eV for pMOS.
官方說明文件#: NSC95-2221-E009-298-MY3
URI: http://hdl.handle.net/11536/102113
https://www.grb.gov.tw/search/planDetail?id=1584358&docId=271490
顯示於類別:研究計畫