利用齊納接面改善氧化矽/氮化矽/氧化矽堆疊式快閃記憶體之特性

Abstract

目前論文的題目主要是以探討在現今被廣泛使用的浮動閘極非揮發性記憶體。就快閃記憶體而言，通常會遇到兩個問題：首先是在元件的穿隧氧化層厚度小於10奈米時，雖可改善快閃記憶體的讀寫速度，但電荷保存時間亦隨之下降。再來是經過多次讀寫後在穿隧氧化層品質容易劣化而產生漏電路徑，而一旦有一條漏電路徑產生，所有儲存在浮動閘極的電荷都會經由此漏電路徑而全部流失掉，這也是目前浮動閘極非揮發性記憶體最嚴重的問題。 氧化矽/氮化矽/氧化矽堆疊式結構的記憶體元件，是使用氮化矽作為電荷陷捕層，在此種結構內，因為電荷是被儲存在分離式的陷捕位置中，故可改善在浮動閘極結構中對於資料保存性的問題。但是因為氮化矽與穿隧氧化層之間的導電帶位能差太低，會使得元件的寫入/抹除速度降低，而現在記憶體的基本要求不外乎在加快寫入/抹除的速度，增加資料保存的期限，在連續的寫入/抹除的重複性動作下，去提升元件對此動作的忍受度。 而在本篇論文中，我們將在源極端和汲極端形成一個齊納接面，利用齊納接面的特性去改善傳統氧化矽/氮化矽/氧化矽堆疊式快閃記憶體的寫入及抹除的特性。 在本篇論文的第二章中，首先探討不同條件的齊納接面對P型基板之堆疊式記憶體元件的寫入及抹除速度帶來的影響，並且進一步觀察此齊納接面是否對元件其他的特性有負面影響，並分析元件特性的原理。 在本篇論文的第三章中，探討不同條件的齊納皆面對N型基板之堆疊式記憶體元件的寫入及抹除速度產生的影響，並同時觀察記憶體其他特性，受到齊納接面結構影響後，是改善或者劣化，最後會分析元件特性的原理。 在本篇論文的第四章中，會做一個簡單的結論，比較N型通道和P行通道之間的優缺點。

The topic of the paper is the floating gate non-volatile flash memory which is extensively used in the present. For the non-volatile flash memory, there are two problems： First, when the thickness of tunneling oxide is scaled down to 10 nano-meter, the programming speed of flash memory is improved, but the retention time is decreased. Second, after the programming and erasing operation cycles, it will cause the tunneling oxide damage and make the oxide quality degradation. The oxide damage would generate a leakage path which will cause the charges stored in floating-gate layer lost by the leakage path. The leakage issue is the most serious problem of the floating-gate non-volatile flash memory. In order to solve the leakage path problem, we use the silicon-oxide/silicon-nitride/silicon-oxide stack structure memory device. The silicon-nitride layer is used to be the charge trapping layer. Because the charge stored in the trapping is in the discrete trapping site in the stack structure device, it can improve the data retention reliability compared with the floating-gate flash memory. Because of the difference of conduction band between silicon-nitride trapping layer and silicon-oxide tunneling layer is too small, the programming speed and the erasing speed of the stack structure will decrease. But the operation speed, well data retention reliability, and the endurance of the device under the stress by the repeated program and erase cycles in the memory device are the most important requirements. In the thesis, we will form a Zener junction at the source side and the drain side, then we employ the Zener junction to improve the program and erase characteristic of SONOS stack structure memory. In the Chapter 2, we will use the different dose of boron doping to perform the reverse halo implantation. Then we would discuss the effect on the programming speed and the erasing speed of P-type substrate SONOS memory with the different condition of the Zener junction. Finally, we will observe if the Zener junction caused the degradation on the other characteristics of memory, and explain these phenomenons further. In the Chapter 3, we will talk about the effects on the characteristics of the n-type substrate SONOS memory , especially on the programming and erasing speed. We use the different does of phosphorus doping to accomplish the reverse halo implantation. And we would observe the characteristics of SONOS memory such as programming speed, erasing speed, data retention, endurance, and so on. Finally, we will find the theorem to explain the phenomenon. At last, we will give an conclusion in Chapter 4.