矽基板上新穎結構的非揮發性記憶體與互補式金氧半場效電晶體的研究

Abstract

此論文在傳統矽基板上製做不同的新型結構元件，包含了非揮發記憶體與基板分割的場效電晶體。 首先，我們使用不同的結構來製做非揮發記憶體。傳統上，非揮發記憶體的閘極絕緣體堆疊結構為氧化矽－氮化矽－氧化矽，與單純一層氧化矽製做的邏輯元件有很大的差距。在我們的結構中，閘極電極下方與邏輯元件一樣只有單純一層氧化矽，而電荷捕捉層是由矽酸鉿退火型成的奈米微晶粒構成，此捕捉層的位置是在氮化矽的隔離層下方。而此隔離層下方並沒有源極╱汲極的任何離子佈植。此結構的記憶體提供了寫入與抹除的特性，我們也會討論此元件的資料持久性與抗干擾的能力。這種結構的非揮發記憶體對於未來希望在同一晶片上製做非揮發記憶體與邏輯元件的技術是非常有潛力的。若能把非揮發記憶體與邏輯元件製做在同一晶片上，可以有效提升系統的速度。 接著，我們在矽基板上製做了n型場效電晶體。這種三通道閘極的結構通常使用在絕緣體上矽基板上。我們發現蝕刻小部分的淺溝槽隔離氧化矽可以有效的改善元見的次臨界擺幅。並且可以降低臨界電壓。在本體效應的量測中，我們發現在比較窄的閘極寬度或是蝕刻比較深的淺溝槽隔離氧化矽之下，本體的電壓對通道的影響會受到側壁的空乏區的影響而阻隔。 最後，我們製做了同樣結構的p型場效電晶體。這些p型場效電晶體，與ｎ型場效電晶體有類似的電性趨勢，在某些部份改善了電晶體的電性。因此在矽基板上製做的三通道元件可以改善ＣＭＯＳ元件的特性。

In this thesis, we fabricated non-typical devices on the silicon bulk for nonvolatile memory and segment-MOSFET. First, we will present a novel nonvolatile flash memory process with only silicon oxide under the gate electrode instead of the oxide-nitride-oxide structure. The storage layer, which is fabricated by hafnium silicate (HfSiOx) as the trapping material, is deposited under the nitride spacer. No LDD dopant is implanted under the spacer stack, so there is no overlapped region between source/drain and gate electrode. These nonvolatile memories exhibit programming characteristics and erase characteristics. Also the retention and disturbance characteristics of these devices will be discussed. Since the fabrication process of the nonvolatile memory is similar to the logic device, the structure will become attractive if it is possible to fabricate the nonvolatile memory embedded with the logic device. Next, we fabricated the segment n-MOSFET on the silicon bulk. The FINFET structure is usually fabricated on the SOI wafer. We found that the recess of shallow-trench-isolation oxide enhances the subthreshold swing characteristics and decreases the threshold voltage, and the body voltage is blocked during the body effect measuring. Finally, the segment p-MOSFET was fabricated with the same process as the segment n-MOSFET. The trend of p-MOSFET is similar to n-MOSFET, so the FIN structure also improves some performance on silicon bulk for CMOS process.