標題: | 用於 UWB 及 WIMAX之雙模通道等化器設計 Dual mode Channel Equalizer Design for UWB and WIMAX Systems |
作者: | 葉柏麟 Po-Lin Yeh 溫瓌岸 Kuei-Ann Wen 電子研究所 |
關鍵字: | 通道估測;頻域等化器;相位追蹤器;適應性通道追蹤器;載波頻率漂移;取樣時脈漂移;Channel Estimator;Frequency Domain Equalizer;Phase Error Tracker;Adaptive Channel Tracker;Carrier Frequency Offset;Sampling Clock Offset |
公開日期: | 2007 |
摘要: | 本論文提出一適用於IEEE 802.15.3a與IEEE 802.16d雙規格的通道等化器,此通道等化器包含通道估測,頻域等化器,相位追蹤器,適應性通道追蹤器等,用以解決正交分頻多工系統上,存在之多路徑通道,加成性白色高斯,射頻傳輸器與接收器之本地訊號不匹配以及D/A與A/D之取樣頻率不匹配等非理想效應。
經由完整的UWB系統模擬,所提出的方法在不同的傳輸環境下,可達到1.36~7.25dB的SNR系統效能增益,WIMAX的系統方面,另提出的適應性通道追蹤器,可有效減少通道估測誤差,經由模擬,提出的方法可降低3~18 dB的通道估測方均誤差(MSE),在不同的傳輸環境下,也可獲得0.5~3.9dB的SNR系統效能增益。
為了處理雙模的訊號,採用了通用於兩種系統規格的演算法,電路設計上得以運用通用的運算單元,以提升使硬體使用效率,藉由Synopsys Design Complier 合成,在UMC 0.18 um CMOS的製程環境下,所提出的設計僅需13萬邏輯閘,另外為了符合UWB 528Msamples/s的資料處理速度,電路上採用了兩倍平行度的設計,使其輸出量最快可達到540百萬取樣。 In this thesis, a dual mode channel equalizer is proposed for applications on IEEE 802.15.3.a and IEEE 802.16d. The proposed channel equalizer comprises channel estimator, frequency domain equalizer, phase error tracker, and adaptive channel tracker. It is applied to resolve non-ideal effects, such as multi-paths channel, additive white Gaussian noise, carrier frequency mismatch between RF transmitter and receiver, sampling clock mismatch between digital-to-analog converter and analog-to-digital converter in Orthogonal Frequency Division Multiplexing (OFDM) system. Through complete UWB simulation, the proposed channel equalizer can obtain 1.36 ~7.25dB gain in signal-to-noise ratio (SNR) for different transmission conditions. In WIMAX system, the proposed adaptive channel tracker can reduce channel estimation error effectively. With system simulation, the proposed adaptive channel tracker can reduce the mean-square-error of channel estimation by 3~18 dB. Under different transmission conditions, the proposed methodology can obtain 0.5~3.9 dB SNR gain. In order to deal with dual-mode signals, common algorithms are selected to process both UWB and WIMAX signals. With common Algorithms, common architectures can be designed to obtain hardware efficient. Design is synthesized to UMC 0.18um CMOS standard cell technology library with Synopsys Design Compiler. The total gate count is merely 130k. Finally, in order to meet the sampling rate of 528Msample/s for UWB, the proposed channel equalizer uses two-parallelism and throughput can achieves 540M samples per second. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009511637 http://hdl.handle.net/11536/38160 |
顯示於類別: | 畢業論文 |