應用於正交分頻多工為基礎的無線存取系統之低複雜度頻率同步器

Abstract

在達到高資料傳輸率及低功率消耗的無線基頻設計上，使得能有效的應用在高速及攜帶式的無線通訊產品。而近年來，超寬頻技術被發展成應用在高速資料傳輸上，如無線USB 2.0等。 而在解決頻率漂移的頻率同步器上，為了達到高於500MSamples/s 的處理能力，我們採用了平行化的架構。因此目前頻率同步器的主要挑戰即為在達到高速的情況下，降低其複雜度並且保持系統的效能。本論文的主旨即針對以正交分頻多工為基礎的無線存取系統而設計一個低複雜度之頻率同步器。此設計結合了以資料分割為基礎的相關性演算法，power aware的概念以及近似特性的補償機制。而設計本身則提供了一個可以減少不必要的運算量同時達到系統可接受的效能損失的方法。甚至，我們可以在環境較好的情況下，利用power aware的概念來減少更多的功率消耗。基於資料分割的演算法，我們可以用單一路徑的頻率同步器來達到528MSamples/s的處理能力及480Mb/s的資料傳輸率。而由模擬結果可得知，在達到10% PER的IEEE 802.11a WLAN 系統下和8% PER的 LDPC-COFDM及MB-OFDM UWB的系統下，其效能損失可以限制在0.6dB SNR以下。而設計實現後，在達到528MSamples/s處理能力下，其功率消耗在0.18μm製程中可以減少到原本傳統設計的69.4% ~ 75.6%。

The wireless baseband design achieving high data rates and low power dissipation leads the high efficiency of transmission speed and battery life of wireless access applications. Recently the ultra-wideband (UWB) is hotly developed for hundreds Mb/s speed and wireless USB 2.0 applications. In the baseband frequency synchronizer, which solves the carrier frequency offset (CFO), needs to be the parallel architecture to stably achieve > 500MSamples/s throughput rate. Hence the main challenge of the present frequency synchronizer design becomes simultaneously achieving high throughput rate, low hardware complexity, low system packet error rate (PER) demanded by UWB system. In this thesis, a low complexity frequency synchronizer comprises data-partition-based correlation algorithms, power-aware concept and approximate compensation scheme is proposed for OFDM-based wireless access systems. It provides a methodology to reduce redundant computation complexity with an acceptable performance loss; and further, we can reduce more power consumption in the better channel condition by concept of power-aware. Based on data-partition algorithm, a single-path frequency synchronizer with parallel CFO compensators is developed to achieve 528MSamples/s throughput for the 480Mb/s UWB design. Simulation results show the synchronization loss of the proposed design can be limited to 0.6dB SNR for 10% PER of IEEE 802.11a WLAN system and 8% PER of LDPC-COFDM and MB-OFDM UWB systems. The implementation result shows the proposed low-complexity scheme achieving 528MSamples/s throughput rate can reduce 69.4% ~ 75.6% power consumption of a conventional parallel approach in 0.18μm CMOS process.