三模MIMO之無線區域網路等化器設計

Abstract

本論文提出一個可操作在具兩個傳送天線與兩個接收天線的三模等化器(Equalizer)。所提出的三模等化器，在高速的無線區域網路(Wireless LANs)中，可操作模式包含SISO模式、SDM-MIMO模式和STBC-MIMO模式共三個模式。為考慮載波頻率偏移(Carrier Frequency Offset, CFO) 對系統的影響，本論文提出一個方法來有效率的減緩剩餘載波頻率偏移(Residual CFO)所造成的影響，以降低通道估測的錯誤。接著，提出一個高效率的載波頻率偏移追蹤器可以有效的降低系統封包錯誤率(Packet Error Rate)。 模擬結果顯示使用上述的方法可以在2x2多重輸入多重輸出(Multi-Input Multi-Output)的系統中，將剩餘載波頻率偏移對封包錯誤率的影響減低至0.2dB以內。考慮到實際的硬體實現，先觀察在三個模式中所使用演算法的相似度，在所提出的三模等化器架構中大量使用共用架構來減少面積消耗。最後，我們使用FPGA來實現所提出的電路。

In this thesis, an efficient hardware architecture for tri-mode equalizer with two transmit and two receive antennas is proposed. The proposed tri-mode equalizer supports SISO, SDM-MIMO and STBC-MIMO for wireless LANs is designed. Considering the effects of carrier frequency offset (CFO), an effective CFO mitigation method is proposed to reduce the channel estimation error caused by residual CFO. Then, an effective CFO tracking algorithm is also proposed to enhance packet error rate (PER) performance. Simulation results show that the proposed CFO mitigation and tracking algorithm can effectively suppress the PER performance loss due to residual CFO within 0.2 dB in the 2x2 multi-input multi-output (MIMO) system. For practical implementation, a lot of shared-architectures are utilized to reduce area consumption of the tri-mode equalizer by observing the similarity in the algorithms of the three modes. FPGA is used to implement our design.