標題: 應用於正交分頻多工系統之以記憶體為基礎之高效率任意長度快速傅立葉轉換器設計
A Memory Efficient General-size FFT Processor for OFDM Communication Systems
作者: 蕭清峰
Chen-Fong Hsiao
李鎮宜
C. Y. Lee
電子研究所
關鍵字: 快速傅立葉轉換;以記憶體為基礎;質點數;FFT;memory-based;prime-sized
公開日期: 2007
摘要: 在這一篇論文裡面,一個一般化的混和基數演算法被提出來,以設計可以同時支援質點數與傳統2n點數的以記憶體為基礎之快速傅立葉轉換器。在此,我們把指標轉換成多維度指標向量。藉由控制這些指標向量來執行向量反轉的行為,在不產生記憶體存取衝突的前提下,我們可以達成以資料置換的方式來存取資料以減少所需要的記憶體,並且同時支援多記憶體結構來減少處理器所需要的執行時脈速度。 在處理器的硬體設計方面,我們提出了一個低硬體複雜度的指標向量產生器來支援我們提出的演算法。同時,我們也把數個短點數的FFT功能有效的整合到一個計算單元裡面。接著,我們藉由上面提出的模組,有效率的實現了可變長度的快速傅立葉轉換處理器來支援不同標準的數位傳播系統的應用。此處理器可以同時支援2048,4096,8192以及3780點的快速傅立葉轉換。在此,我們把3780點這規格也給納入的原因是因為這規格已經被中國的數位電視訂為標準規格了。此外,如果我們考慮3780點傅立葉轉換器的設計,我們所提出的方法可以在不損失效能的前提下,比目前現有的方法還大量的減少硬體面積。
In this thesis, a generalized mixed-radix (GMR) algorithm is proposed for memory-based fast Fourier transform (FFT) processor to support prime size FFT and traditional 2n-point FFT simultaneously. It transforms the index to a multi- dimensional vector. By controlling the index vector to satisfy the “vector reverse” behavior, it could support not only in-place policy to minimize the necessary memory size, but also multi-bank memory structure to reduce necessary clock rate without memory conflict. For processor design, a low complexity hardware implementation of index vector generator is proposed for our algorithm. Several smaller size FFT functions are integrated within a computational unit. By applying above into our design, a hardware efficient variable length FFT processor is proposed for different standard DTV applications. It can support 2048/ 4096/ 8192/ 3780-point FFT. The reason of 3780-point FFT is it has been adopted as the standard of Chinese DTV application. Moreover, if we only take the 3780-point FFT into account, our work can reduce the hardware cost significantly than previous methods.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009511650
http://hdl.handle.net/11536/38172
Appears in Collections:Thesis