應用於處理器驗證之腳本導引的限制隨機樣本產生器

Abstract

積體電路設計複雜度的快速成長使得整個設計流程所需的時間也跟著拉長，但是在受到上市時間的限制下，縮短開發時程是必須的。在設計過程中驗證這步驟大約佔了全部時程的60%至70%，發展新的驗證策略來縮短產品推出的時程是相當重要的。標準參考模型和直接測試在現今的驗證環境中變為基本的方法。驗證策略必然朝向更新的方式，例如以有限制的隨機生產方式來縮短測試樣本的發展時間，進而加快完成積體電路的完整驗證。針對某些被微處理器設計者忽略的不常發生的情境與狀況，以有限制的隨機生產方式產生相對應的測試樣本達到在驗證階段的初期就能及早發現設計的錯誤。在本論文中，詳細的介紹了有限制的隨機生產器以及如何利用我們提供的命令文件(script file)便能簡單地針對指定的情況製造出大量的測試樣本。

IC complexity is increasing so rapidly that the time spent on whole design flow increases in this situation. It is necessary to reduce the development time due to the pressure from the time to market. Verification presents about 60-70% of the total design effort and advances in verification methodology can improve the time to market considerably. Directed tests and golden reference models are becoming the primitive tools in the modern design verification environment. Verification strategies are consequently developed towards advance methodologies like constrained-random approach to reduce verification pattern development time, and speed up the time it takes to achieve complete verification. Constrained-random pattern generation tools create tests for corner cases that the microprocessor designers may not expect and hence find bugs early in the verification stage. This thesis describes the details of the constrained-random generator and the script file that helps easily produce a huge amount of constrained-random patterns for designated corner cases.