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dc.contributor.author莊立溥en_US
dc.contributor.authorLi-Pu Chuangen_US
dc.contributor.author黃威en_US
dc.contributor.authorWei Hwangen_US
dc.date.accessioned2014-12-12T01:14:11Z-
dc.date.available2014-12-12T01:14:11Z-
dc.date.issued2007en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009511671en_US
dc.identifier.urihttp://hdl.handle.net/11536/38193-
dc.description.abstract本論文提出一個全數位式快速鎖定具自我校正功能的多相位延遲鎖定迴路設計。根據所提出的快速自我校正演算法,減少因為製程不相配或是輸出負載不同造成輸出訊號的相位誤差。此外,為了達到快速鎖定,以及增加操作頻率範圍並且同時避免多諧鎖定,提出了一個非平衡式二進位搜尋演算法,其特點在於提供不同的初始延遲時間已達到上述的功能。一個非平衡式二進位搜尋控制器實現在UMC 90nm CMOS技術,模擬結果顯示,當延遲鎖定迴路操作頻率在100MHz到500MHz (五倍)時,可以在22個參考時脈週期內鎖定(最差情況)。 一個300MHz到1.08GHz全數位精確多相位輸出延遲鎖定迴路實現在UMC 90nm CMOS技術。藉由一新型數位控制線性近似延遲元件達到線性增加延遲時間以及抗環境變異的能力。一個數位式校正單元根據所提出的快速自我校正演算法被設計與實現並且能使多相位輸出訊號的相位誤差自我校正。在校正程序結束之後,校正單元會自動關閉以減少功率消耗。在操作頻率為500MHz時,最大相位誤差可從20.9ps減少至4.5ps。其最大消耗的總功率為2.16毫瓦當操作在1GHz時。本論文提出的延遲鎖定迴路可穩定地使用在各種嵌入式記憶體應用。zh_TW
dc.description.abstractAn all-digital fast-lock self-calibrated DLL is proposed in this thesis. Base on the proposed rapid self-calibration (RSC) algorithm, the timing error caused by process mismatch and various output loading can be effectively self-calibrated. Besides, an unbalance binary search algorithm is proposed to extend the locking range and avoid harmonic lock at the same time. An unbalance binary search algorithm based (UBS) controlled is implemented in UMC 90nm CMOS technology. The simulation results show that, the operating frequency is 100MHz to 500MHz (up to 5X) and the lock-in time is down to 22 reference clock cycles in the worst case. A 300MHz-1.08GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with UMC 90nm CMOS technology. The linear approximate delay element property of linearity and insensitive to PVT variation is good for digitally controlled delay line. In addition, a digital calibration unit is designed based on RSC algorithm, which makes the phase error among the multiple outputs can be self-calibrated. The entire calibration unit could be turned off after calibration procedure is complete to reduce power consumption. The simulation results show the DLL exhibits a lock range from 300MHz to 1.08GHz. The maximum phase is reduced from 20.9ps to 4.5ps when the DLL is operating at 500MHz. The total power dissipation of the all-digital self-calibrated multiphase delay-locked loop is 2.16mW at 1GHz with 1V power supply. The presented DLL can be robustly used in embedded memory applications.en_US
dc.language.isoen_USen_US
dc.subject延遲鎖定迴路zh_TW
dc.subject自我校正zh_TW
dc.subject多相位zh_TW
dc.subjectDLLen_US
dc.subjectself-calibrateden_US
dc.subjectmultiphaseen_US
dc.title全數位快速鎖定自我校正多相位延遲鎖定迴路zh_TW
dc.titleAn All-Digital Fast-Lock Self-Calibrated Multiphase DLLen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis


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