應用於行動式視訊裝置之嵌入式壓縮器解壓縮器設計

Abstract

本論文提出適合嵌入於行動式視訊裝置上的有失真嵌入式壓縮器/解壓縮器設計。藉由有失真資料壓縮來減少晶片與外部記憶體間所需要的資料傳輸量，損失些微的視訊品質，來達到縮小外部記憶體空間需求、減少頻寬使用以及降低能量消耗等多種目的。 所提出的演算法是以二維離散餘弦轉換搭配簡約位元平面區域編碼所構成。在壓縮率為二的前提之下，將一個四乘以四的像素矩陣壓縮為六十四位元的壓縮封包。首先將四乘以四像素矩陣以二維離散餘弦轉換為十六個不同頻率之係數分量，再使用簡約位元平面區域編碼將係數予以編碼封存後送到外部記憶體。解壓縮過程中並提出一個簡單的補償方式來彌補失真壓縮所造成的資料遺失。 所提出的硬體架構可以嵌入在視訊解碼器上以100MHz的操作頻率支援每秒三十張的高畫質電視規格(HD1080)。由於將壓縮率固定為兩倍，所以壓縮後的封包大小固定，記憶體地址轉換十分簡單並且可以支援動作補償單元 (Motion Compensation)的亂數存取。在UMC 90奈米製程技術下，所提出的硬體使用了30k個邏輯閘數目。壓縮一個巨型區塊(MB)需要72個週期，解壓縮一個巨型區塊(MB)則僅需要34個週期。整體系統對於記憶體的存取次數則節省了原本的百分之四十。相較於所消耗的功率，節省的功率相當的可觀。

This thesis proposes an embedded compressor/decompressor for mobile video applications. It uses lossy compression scheme to reduce the amount of data transferring between chip and external memory. This lossy compression can maintain acceptable video quality while reduces the required size of external memory, the bandwidth requirement and the power consumption on memory access. Proposed algorithm is composed by discrete cosine transform (DCT) with coarse grain bit-plane zonal coding (CGBPZ). The compression ratio is two. It compresses a 4x4 pixel-array into a 64 bits segment. First, the two dimensions discrete cosine transform converts 16 pixels into 16 elementary frequency components. Coarse grain bit-plane zonal coding packets the coefficients and then sends to external memory. A compensation scheme is also proposed for decoding. Hardware architecture of the proposed algorithm is able to be embedded into video decoder and support HD1080@100MHz, 30 frames per second. Since the compression ratio is fixed at two, the coded segments have fixed size and can be randomly accessed by motion compensation unit. The gate counts are 30K synthesized by UMC 90 nm CMOS technology. It costs 72 cycles to encode a MB and 34 cycles to decode a MB. Overall reduction ratio on memory access is 40%. Comparing with the power consumed of proposed design, the amount of power saving is large.