WiMAX 通道編碼技術與數位信號處理器實現之探討

Abstract

IEEE 802.16e 無線通訊標準中，於系統的傳送端訂定了前向誤差改正編碼的機制，藉此減低通訊頻道中雜訊失真的影響。通道編碼是本論文的重點。

本篇論文前半部份重點在於，研究IEEE 802.16e OFDMA所訂定的迴旋編碼(咬尾)系統並且實現在德州儀器公司所發展數位訊號處理器(DSP) TMS320C6416上的維特比解碼協處理器(VCP)並針對咬尾編碼的特性，中斷服務常式(ISR)以及增強型直接記憶體存取(EDMA)進行研究。此外我們也利用3L Diamond的EDMA進行VCP在多個DSP運算處理的應用。在論文中，我們利用C語言所模擬的迴旋碼在加成性白色高斯通道下和利用VCP應用於迴旋碼進行效能及速度上的比較。在效能錯誤率上，受限於實點數及VCP輸入位元數的硬體條件下，若以相同條件比較而言，兩者的效能是接近的。而在速度方面，經過在DSP平台上最佳化我們的程式後，分別於CCS 模擬器和3L測量上，迴旋編碼的編碼器部份，可以到每秒16,667K和3,764K位元的處理速度，而在VCP方面解碼器的部份可以達到每秒7,897K和2,997K位元的處理速度，C語言模擬方面則可以達到每秒805K和632K位元的處理速度。簡而說之，若以解碼器觀點而言，VCP提升了速度為9.8和4.7倍，分別針對CCS模擬器和3L Diamond測量而得到數據。

本論文後半部份重點，研究IEEE 802.16e OFDMA所訂定的渦輪迴旋碼(CTC)系統並且實現在數位訊號處理器。闡明渦輪迴旋碼的雙二位元循環遞迴系統迴旋(duo-binary CRSC)編碼與最大對數事後機率(max-log MAP)解碼演算法。我們利用C語言驗證系統演算法上的正確性，並在加成性白色高斯通道下模擬了各種調變。接著在TI C6416 DSP平台實現，於3L Diamond測量上方面，編碼器部份可以到每秒8,223位元的處理速度，而解碼器的部份僅可以達到每秒30K位元的處理速度。之後我們對於解碼器做了一些最佳化的改善，使解碼器的速度增進約10倍，進而可以達到每秒300K位元的處理速度。

In the IEEE 802.16e wireless communication standard, a forward error correction (FEC) mechanism is presented at the transmitter side to reduce the noisy channel effect. The focus is on the channel coding.

The focus of the fist part of this thesis is the research of the convolutional code (CC) with tail biting defined in IEEE 802.16e OFDMA standard and implement the project on Viterbi-decoder coprocessor (VCP) of the Texas Instruments (TI)’s TMS320C6416T digital signal processor (DSP) and also sturdy for tail-biting encoding property, interrupt service routine (ISR) and enhanced direct memory access (EDMA). Besides, we also employ the EDMA under 3L Diamond real-time operating system (RTOS) for the VCP applications of multi-DSP operation. We compare CC in AWGN channel on the C program to CC on the VCP applications for BER performance and processing rate. In BER performance, the simulation is limited to the hardware fixed-point and VCP branch metric input bit numbers; however, if we utilize the same condition to compare them, we can find their performance are close. In processing rate, after optimizing the programs on the DSP platform, encoder can achieve two data processing rates of 16,667 Kbps and 3,764 Kbps, the VCP decoder can achieve two processing rates of 7,897 Kbps and 2,997 Kbps and the C program decoder can achieve two processing rates of 805 Kbps and 632 Kbps, respectively on the C6416 CCS simulator and 3L Diamond. In short, we utilize the CCS and 3L to measure, finding decoding processing rate can be improve significantly about 9.8 and 4.7 times, respectively.

The focus of second part is the research of the convolutional turbo code (CTC) defined in IEEE 802.16e OFDMA and implement on the C6416 DSP. We explain the duo-binary circular recursive systematic convolutional encoding (duo-binary CRSC) and the max-log MAP decoding algorithm. We employ the C program to insure the correctness of our algorithm and simulate the CTC for different modulation in AWGN; then, we implement on TI C6416 DSP. The encoder can achieve a data processing rate of 8,223 Kbps and the decoder can achieve a processing rate of 30 Kbps on the 3L. Then we utilize some optimized techniques to improve the decoder's speed, which is approximately 10 times speeded up in decoding rate. Therefore, the decoder can achieve a further data processing rate of 300 Kbps.