抑制熱載子劣化效應與閘極氧化層過壓之混合電壓輸入輸出緩衝器設計

Abstract

傳統輸出輸入介面電路部分金氧半電晶體容易在接收與傳送的轉態過程，在汲極與源極端產生過大壓差，造成熱載子劣化效應，由於製程演進，電晶體通道長度逐漸縮短，使得通道上電場強度越來越大，因此熱載子劣化對電晶體造成的影響遞增，元件的使用年限也隨劣化的嚴重程度而縮短。此外，在汲極與閘極以及源極與閘極間如何避免壓差過大導致閘極氧化層過壓問題也成為元件尺寸下降後，在可靠度電路設計上所需面臨的挑戰。 因此在本篇論文中提出了一個具兩倍電壓耐受度之輸出輸入緩衝器，包含串疊傳輸閘電路(stacked transmission gate) 與利用額外電路提供新接點以解決傳統輸出輸入介面電路過大壓差之現象之新構想，並藉直接引用N-well 極的電壓當作閘極的一種控制邏輯簡化其電路設計上的複雜度且達到較好的面積效 能。新提出的緩衝器已實現於1.2 伏0.13 微米互補式金氧半製程，用以操作在1.2V/2.5V 的混壓式介面下，其輸出頻率可達133MHz。

Rapid development of complementary metal oxide semiconductor (CMOS) techniques desires the transistor dimension to scale down with lower supply voltage continually for reducing chip area, increasing operating speed, and diminishing power consumption. When thickness of gate oxide becomes much thinner and the length of MOS transistor becomes shorter corresponding to smaller device size, the decreasing maximum tolerable voltage across the transistor terminals makes the design of mixed-voltage I/O buffer facing reliability problems such as gate-oxide reliability, hot-carrier degradation, and undesired circuit leakage paths with input signal higher than the voltage level of supply voltage. In this thesis, a new 2xVDD-tolerant I/O buffer circuit, realized with only 1xVDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is presented. The new proposed 2xVDD-tolerant I/O buffer has been implemented in a 130-nm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by the experimental results with a signal speed of up to 133 MHz for PCI-X application. Performances as power consumption and the robustness for hot-carrier degradation and gate-oxide overstress are also compared with a few conventional designs.