模組化在積分三角類比數位器中由有限與非線性運算放大器增益所產生之非線性諧波失真

Abstract

本篇論文目的在於推導一個不同以往可用於三角積分器最佳化設計之積分器快速諧波失真模型,本篇論文詳細分析了積分器非線性特性進而獲得完整的非線性積分器非線性直流增益諧波失真數學模組,更由於主要的諧波失真來自於第一級的積分器,所以我們的數學模組可廣泛應用在各種不同積分三角數位類比轉換器的架構,一般常見的論文為了達到低功率消耗與系統高解析度的設計,往往直接提高過多的直流增益值或消耗大量的最佳化時間,這在現今要求高效率與低耗能的產品要求下,是非常不利於設計者的.為了證明我們的模組不但比傳統的模型快速而且結果能讓設計者使用,最後我們將同時利用行為模組以及電晶體電路實際去驗證我們的諧波失真模型是可以在最快速的運算下,得到設計者想要的最佳化結果.

The purpose of this paper is to introduce a new modeling of op-amp induced harmonic distortion in sigma-delta modulator, which is aimed to optimum design of SDM for high-performance applications. We analyze complete nonlinear characteristic in integrator to obtain analytic models to represent harmonic distortion as function of op-amp nonlinear DC-gain. Our model can apply for all modulator architectures where harmonic distortion is dominated by the first integrator in the chain. In order to achieve the low-power requirement and high-resolution, general approaches adopt either time-wasting model or high-power DC-gain. We show that results provided by our distortion model fit well to that obtained by simulation in behaving model and transistor level. It is accurate and fast than provided by previously reported modeling approaches.