應用於60GHz覆晶封裝系統毫米波接收機之分析與設計

Abstract

本論文主要研究60 GHz頻帶應用的接收機電路，並且它相容於覆晶封裝系統。我們依序設計了60 GHz x4次諧波混頻器、60 GHz x2次諧波混頻器、60 GHz 放大器結合次諧波混頻器、60 GHz 放大器結合次諧波混頻器與本地振盪鏈、60 GHz鏡像訊號消除混頻器結合本地振盪鏈、60 GHz接收機，其中前面四個電路是以WIN 0.15μm PHEMT製程來實現，最後兩個電路是以WIN 0.15μm MHEMT製程來實現。 本論文的混頻器主要是以反對稱二極體對來作為混頻核心，放大器是基於小訊號S參數來做設計，在接收機中我們設計了一個本地振盪訊號鏈來降低系統需求，此振盪鏈的倍頻核心也是反對稱二極體對，並加上一個回授放大器來驅動次諧波混頻器。

In this thesis we study a receiver which is for 60 GHz band applications, and it is compatible of flip-chip mounting system. We designed 60 GHz sub-harmonic x4 mixer, 60 GHz sub-harmonic x2 mixer, 60 GHz amplifier cascades sub-harmonic x2 mixer, 60 GHz amplifier cascades sub-harmonic mixer and LO chain, 60 GHz image-rejection mixer combines with LO chain, and 60 GHz receiver in sequence. We used WIN 0.15μm PHEMT process to implement the former four circuits, and WIN 0.15μm MHEMT process to implement the later two circuits. The mixer core in our thesis is the Anti-Parallel Diode Pair (APDP) mixer, and the amplifier is designed based on small-signal S parameters. In the Receiver, we designed a LO chain to lower the system LO signal requirement, the multiple core of the LO chain is APDP too, and we cascaded a feedback amplifier to drive sub-harmonic mixer.