應用於動態頻率延展之延遲迴路式時脈產生器設計與分析

Abstract

高速輸入輸出介面以及無線通訊系統中需要低成本、高效能的時脈產生器。傳統的做法是使用鎖相迴路(Phase-Locked Loop)來產生時脈。在鎖相迴路中，震盪器使用電感電容共振腔(LC-tank)的方式能減低相位雜訊達到符合高品質的無線通訊系統的效能規範，但是付出了面積與電源消耗的代價。而且電感電容共振腔的數值一旦決定，倍頻係數就無法更改。環形震盪器擁有較低複雜度以及較容易積體的好處而使於用積體化的鎖相迴路，於是成為最受歡迎的震盪器之一。很不幸環型震盪器在相位雜訊的表現上不佳，因此在高品質的通訊系統應用上成為阻礙。 相較於鎖相迴路的做法而言，使用延遲鎖定迴路(Delay-Locked Loop)來產生時脈能產生較低的時脈抖動，這是由於延遲鎖定迴路沒有抖動累積(Jitter Accumulation)的問題。再者，較簡單的迴路濾波器讓延遲鎖定迴路式的時脈產生器佔用更小的面積。近期的研究提出使用延遲鎖定迴路式的時脈產生器和本地震盪器，此做法承襲了延遲鎖定迴路相較於鎖相迴路所先天具有的數個優點，用來克服延遲鎖定迴路難以倍頻的問題。我們針對延遲鎖定迴路式為主的時脈產生器做設計與分析，使其達到0.5為基數的倍頻係數，最高達到4倍頻。輸出時脈的操作頻率範圍從150MHz到1200MHz。此時脈產生器甚至在以下的切換情況下只需要一個時脈週期就能完成頻率延展：當倍頻係數之間切換為0.5、1、2、4倍時，或是1.5、3倍時。晶片的實現使用的是TSMC 0.18μm 1P6M CMOS製程。

Low cost, high performance clock generators are required in high speed I/O interface and wireless communication receivers. The conventional clock generation is based on Phase-Locked Loop (PLL). The Oscillator in a PLL by using LC-tank, which achieves high phase noise performance is needed in high-quality wireless communication systems, but it comes with the cost of area and power consumption and the frequency multiplication factor cannot be changed once the LC-tank value is chosen. The ring oscillator for integrated PLLs has the advantages of less complexity and easiness to integrate, and thus becomes one of the most popular oscillators. Unfortunately, the phase noise of ring oscillators is inferior, impeding its use in high-quality communication systems.. Clock generation by Delay-Locked Loop (DLL) is adopted to achieve lower clock jitter than PLL because of no jitter accumulation. Furthermore, it occupies smaller area due to a simpler loop filter. Recently, DLL-based clock generators and a local oscillator have been proposed to overcome the difficulty of frequency multiplication which utilize the several inherent advantages of DLLs over PLLs. We design and analyze a DLL-based clock generator that achieves a 0.5X-based frequency multiplication factor up to 4X and provides the output clock frequency operating range from 150MHz to 1200MHz. Furthermore, the clock generator achieves fast clock frequency scaling in one clock cycle under the situation: the multiplication factors of 0.5X, 1X, 2X, 4X or 1.5X, 3X are chosen. The chip has been fabricated with TSMC 0.18μm 1P6M CMOS technology.