隨機摻雜擾動在奈米級互補式金氧半場校電晶體邏輯電路特性影響之研究

Abstract

半導體的元件持續縮小，製程變異對元件的電特性產生重大的影響，而隨機摻雜物(Random dopant)的影響就是其中最嚴重的效應之一。使用等效原子層級離散摻雜暨量子傳輸方程的大尺度統計運算方法，吾人發展了一套三維度元件模擬技術，研究隨機摻雜在元件通道長度16奈米之平面場效電晶體(MOSFET)引起的電特性擾動。首先我們提出之模擬方法的精確度先與實驗量測數據所校準過，此法成功分析元件的電特性擾動受到隨機摻雜數目(Random-dopant-number)和隨機摻雜物位置(Random-dopant-position)的影響。研究結果顯示，在16奈米閘極通道長度的元件層級中，隨機摻雜將會造成臨界電壓(Vth)約38.5%的擾動量，對閘極電容(Cg)最大會造成有20%的的差異。在數位電路上，我們分析了邏輯閘(Inverter, NAND, NOR)之時間受到擾動的特性。在16奈米閘極長度之平面電晶體中，通道中的隨機摻雜數目由0顆變化到14顆將導致上升時間(rise time)、下降時間(fall time)、低到高延遲時間(tdLH)及高到低延遲時間(tdHL)分別為23.2%、12.3%、73.5%及101.8%的擾動量。吾人提出了兩種壓抑時間特性擾動之方法，一種是改善通道中摻雜之分佈，此法將會壓抑上升時間、下降時間及高到低延遲時間約11.3%, 7.7% and 16.5%之擾動量; 另一種為改變電路結構，一個並聯NMOS之Inverter可以壓抑下降時間、高到低延遲時間及低到高延遲時間約23.6%、33.1%以及8.0%之擾動量，不過由於增加了電晶體的數目，電容因此變大導致平均時間之上升。 總之，吾人使用等效原子層級離散摻雜暨量子傳輸方程的大尺度統計運算方法所發展之三維度元件模擬技術，提供了一個方法來探討由隨機摻雜所導致在數位電路上時間特性的擾動。

With the continuous scaling of the semiconductor device dimension, modeling of device variability has become crucial for the accuracy of timing in circuits and systems. Unfortunately, due to the randomness of discrete dopant position in device, the fluctuations of device characteristics are hard to be modeled in current compact models. In this thesis, a large-scale statistically sound "atomistic" device-circuit coupled simulation approach is proposed to characterize the random-dopant-induced characteristic fluctuations in 16-nm-gate CMOS integrated circuits concurrently capturing the discrete-dopant-number- and discrete-dopant-position-induced fluctuations. First the accuracy of the simulation technique is confirmed by the use of experimentally calibrated transistor physical model. In the 16-nm-gate intrinsic fluctuation simulation, the result shows that the variation of Vth is about 38.5%. The discrete-dopant-position-induced nonlinear maximum Cg fluctuation is about 20% of mean value. The random dopant induced fluctuation in circuit level is also examined. The variations of timing in logic gates (Inverter, NAND, and NOR), for the 16-nm-gate inverter circuit with the number of discrete dopants, varying from zero to 14 in both n-type and p-type MOSFETs, the maximum difference of rise time, fall time, low-to-high delay time, and high-to-low delay time are about 23.2%, 12.3%, 73.5%, and 101.8%, respectively. Two suppression techniques for logic gates are investigated. The improved doping profile have shown the ability to suppress the fluctuation of rise time, fall time and tdHL with 11.3%, 7.7% and 16.5%. The shunted NMOS inverter can suppress the fluctuation of fall time, tdHL and tdLH with 23.6%, 33.2% and 8.0%. However, the increased transistor numbers will increase Cg and lengthen the nominal time. The large-scale statistically sound "atomistic" device-circuit coupled simulation approach we proposed provides an insight into random-dopant- induced intrinsic timing characteristic fluctuations. The function-dependent and circuit-topology- dependent characteristic fluctuations resulted from random nature of discrete dopants has for the first time been discussed.