低溫複晶矽薄膜電晶體的電容特性及模擬

Abstract

近年來，低溫複晶矽薄膜電晶體已引起大量的研究，其應用相當廣泛。低溫複晶矽薄膜電晶體在面板技術的應用上，由於具有高遷移率，而有機會整合面板周邊電路，實現系統面板的目標。當低溫複晶矽薄膜電晶體應用為驅動電路時，交流信號將操作於閘極。因此低溫複晶矽薄膜電晶體對於元件在交流信號下的頻率響應就具有相當大的重要性。

在本篇論文中，使用準分子雷射製作低溫複晶矽薄膜電晶體，利用阻抗分析儀，量測電容－電壓和電容－頻率來研究準分子雷射製作的複晶矽薄膜電晶體。調變在不同準分子雷射能量密度下的複晶矽薄膜品質，觀察電容在不同的閘極偏壓下對頻率的變化。改變元件尺寸大小及製程步驟，來觀察元件特性的變化。由於複晶矽薄膜的品質不同，在複晶矽結晶顆粒較小的時候，可以利用先前研究的模型或是RPI模型，考慮膜內單一能階的缺陷，來解釋元件的電容特性。當複晶矽的結晶顆粒逐漸增大，先前研究的模型或是RPI模型已經不能解釋C-f曲線呈現斜直線的現象，單一能階的缺陷已經不能解釋，應由連續能階的缺陷去解釋。利用Seto模型的觀念，考慮晶粒邊界的能障對載子的影響，成功地建立一個模擬來解釋C-f曲線關係。

In recent years, low temperature polycrystalline silicon thin-film transistors (poly-Si TFTs) have been investigated extensively for their wide applications. Poly-Si TFTs have been studied extensively for their application on system-on-panel (SOP) technology due to the high mobility. The low temperature poly-Si TFTs are operated under gate alternating current signal. Therefore, the studies of frequency response of low temperature poly-Si TFTs under gate alternating signal become very important.

In this thesis, the low temperature polycrystalline silicon TFTs fabricated by the excimer laser annealing (ELA). To research the characteristics of ELA poly-Si TFTs is analyzing the capacitance-voltage (C-V) and capacitance-frequency (C-f) by using impedance analyzer. Here, by adjusting different poly silicon crystalline film qualities due to different excimer laser energy densities, the variation of the measured capacitance under different gate biases is observed. We change the dimension of poly-Si TFTs and the fabrication process to observe the characteristic of devices. As poly-Si grain is small, the capacitance characteristics of the poly-Si TFTs can be described by RPI model or the pre-studies which considering the mono-energetic (single energy level) of the trap. As the grain size becomes larger, RPI model or the pre-studies can not be applied to the case which C-f curve is sideling straight. The mono-energetic response is not able to fit experiment result, and we need to specify a continuous-distributed response time of the trap. Using the Seto’s model, we consider the energy barrier of the grain boundary, and the influence of the carriers. We make a new simulation to express the C-f curve successfully.