具分離控制閘之隱藏式選擇性SONOS NAND記憶體元件之研究

Abstract

我們提出一種新穎的分離式閘極結構於含有隱藏式選擇性閘極之半導體─氧化層─氮化矽─氧化層─半導體記憶體元件於NAND電路陣列結構上，此記憶體元件不僅製程簡單也能符合一般數位邏輯CMOS產品中的嵌入式非揮發性記憶體應用。論文中，我們探討在單一位元胞二位元操作中第二位元擾動效應產生的機制與抑制方式，並得到在操作多位元層級模式於此新穎的分離式閘極結構下，將不需要再考量二位元效應對記憶體元件產生的不理想效應，大大增加了位元判別區間與記憶體元件的可靠度。其中，我們操作此記憶體元件在單一位元胞二位元之多層級操作情況，在寫入與抹除操作的選擇上，我們則分別利用源極端注入(Source-Side-Injection)與能帶到能帶穿隧產生熱電洞(BTBTHH)的機制來完成，其操作在多位元的最低寫入速度仍將少於30us，寫入電流大小則大約是80nA，此時的隱藏式選擇性閘極與字元線控制閘極偏壓分別是0.45V與11V，而最快的抹除速度則可以在8ms被完成。 此特殊的新穎結構中主要的特點是包含了隱藏式選擇性閘極與分離式控制閘極。利用隱藏式選擇性閘極來形成多位元層級操作能得到較快速且精準的寫入過程與低功率消耗的特性；而分離式控制閘極則可以有效的抑制單一位元胞中二位元干擾效應的發生，降低臨界電壓所產生的波動範圍，進而維持一定的位元感測區間。此外，利用最佳化的ONO厚度可以達到非常優秀的抗閘極擾動、抗讀取擾動與長時間資料保存的能力；即使經過一萬次的重覆寫入/抹除的操作後，仍能夠保有原始的臨界電壓窗差值並在位元感測區間的範圍之內，而不會有位元判斷錯誤的結果發生。因此，此記憶體元件非常適合操作在單一位元胞二位元之多層級操作情況，它能擁有快速寫入、高可靠度與低功率消耗的特性表現。

For the first time, we propose the novel Wrapped-Select Gate SONOS (WSG-SONOS) memory with split-control gate in NAND architecture. The memory process is not only simple but also compatible with embedded non-volatile memory in conventional standard logic CMOS products. In this thesis, we demonstrate the physical mechanism and elimination of 2nd bit effect in 2 bit/cell operation. The results show that non-ideal 2nd bit effect would not be a consideration for the novel WSG-SONOS memory device with multi-level operation. It effectively increases the reliability of memory cell for the larger sensing margin of each state. Moreover, we operate the WSG-SONOS memory in 2 bit/cell mode with multi-level operation. The programming and erasing operations are performed by the Source-Side Injection (SSI) and Band-to-Band Tunneling Hot-Hole (BTBTHH), respectively. While operating the memory device in multi-level mode, the slowest program speed would be still less than 30us; the programming current is about 80nA as the wrapped-select gate voltage and word-line gate voltage are 0.45V and 11V, respectively. The fastest erase speed of 8ms is achieved. The main features of this novel device contain the wrapped-select gate and split-control gate. By utilizing the wrapped-select gate to be an assistance gate, the SSI could accomplish the precisely multi-level operation in this memory cell. The SSI programming operation would achieve the low power consumption and high program speed’s characteristics in the memory device. In addition, the split-control gate could effectively decrease the variation of threshold voltage by eliminating the 2nd bit effect disturbance. It would remain the sense margin in this novel memory with multi-level operation. Moreover, the optimum thickness of ONO stack performs excellently for almost no gate disturbance, no read disturbance and long data retention. Even after 10K P/E cycling stress, the error bit wouldn’t happen in such device’s sensing window. As a result, the WSG-SONOS memory with split-control gate in NAND array is very adapted for the 2 bit/cell mode with multi-level operation. It owns the high program speed, low power consumption and high reliability characteristics for the flash memory technology demands. Thus, it has the larger application potential for flash memory market in the future.