完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | HSIAO, PY | en_US |
dc.contributor.author | TSAI, CC | en_US |
dc.date.accessioned | 2014-12-08T15:05:23Z | - |
dc.date.available | 2014-12-08T15:05:23Z | - |
dc.date.issued | 1991-01-01 | en_US |
dc.identifier.issn | 0143-7062 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/3914 | - |
dc.description.abstract | A new application of artificial intelligence techniques in automatic compaction design for a VLSI mask layout is presented. To overcome the shortcomings of iterative search through a large problem space within a working memory, and therefore, to speed up the runtime of compaction, a set of rule-based region query operations and knowledge-based techniques for the plane sweep method are presented in this system. Experimental results have explored the possibility of using expert system technology to automate the compaction process by reasoning about the layout design, applying the sophisticated expert rules to its knowledge base. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | COMPUTER-AIDED DESIGN | en_US |
dc.subject | VERY LARGE SCALE INTEGRATION | en_US |
dc.title | EXPERT COMPACTOR - A KNOWLEDGE-BASED APPLICATION IN VLSI LAYOUT COMPACTION | en_US |
dc.type | Article | en_US |
dc.identifier.journal | IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES | en_US |
dc.citation.volume | 138 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.spage | 13 | en_US |
dc.citation.epage | 20 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:A1991EU14300002 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |