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dc.contributor.authorWU, CYen_US
dc.contributor.authorWU, TSen_US
dc.date.accessioned2014-12-08T15:05:25Z-
dc.date.available2014-12-08T15:05:25Z-
dc.date.issued1990-12-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://dx.doi.org/10.1016/0038-1101(90)90142-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/3955-
dc.description.abstractPhysical timing models have been derived by using the current-domain BJT equivalent circuit for high-speed low-power bipolar NTL circuits. The design methodology of the shunt capacitance C(E) and the emitter length of bipolar NTL circuits has also been developed in this study. It is shown that the optimal value of the shunt capacitance C(E) is equal to 1-1.25 C(E0) where C(E0) is the shunt capacitance of NTL circuit without voltage or current overshooting and undershooting. Both an exact model and a simplified model for C(E0) have been derived. Applying the developed timing models and design methodology, the sizing of NTL gates and taper buffers have been successfully performed as application examples.en_US
dc.language.isoen_USen_US
dc.titlePHYSICAL TIMING MODELS AND DESIGN METHODOLOGY OF BIPOLAR NONTHRESHOLD LOGIC-CIRCUITSen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/0038-1101(90)90142-2en_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume33en_US
dc.citation.issue12en_US
dc.citation.spage1615en_US
dc.citation.epage1627en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1990EP15200014-
dc.citation.woscount0-
Appears in Collections:Articles