在奈米製程下考慮冗餘接點以及保持佈局拓樸原樣的電路遷移自動化技術

Abstract

為了避免人力資源和時間上的浪費，製程遷移自動化技術在細胞函式庫與全客制化積木重新設計的議題上扮演著很重要的腳色，傳統的製程遷移自動化有著會導致佈局物體扭曲與拓樸關係消滅的缺點，這可能會影響到原本佈局的特徵並使得遷移後的佈局難以被使用者所辨認與驗證。在奈米製程，接點是一個使晶片出現缺陷的主因。對於這個問題，晶圓廠建議晶片設計者使用冗餘接點去連接不同層的導線。 這份論文基於前人的架構，在製程遷移過程中保持佈局物體的拓樸關係，另外並加入在製程遷移過程中保留空間的考量使冗餘接點有空間可以插入。遷移的流程包含Y方向以線性規劃為基礎的遷移和X方向以限制圖為基礎的遷移。實驗結果顯示在用我們的細胞函式庫組合出的電路在不增加面積的前提約有40％接點出錯率的改進。另外，胞函式庫的時序差異最多2％。另一方面，藉由使用分數我們在冗餘接點數和細胞函式的面積之間做一個取捨。

To avoid wasting man power and design time, layout migration plays an important role in the re-design of a cell library and full-custom block. Traditional layout migration suffers the disadvantage of shape distortion of objects and destruction to topology between objects. It may alter the features produced by original layout topology and also makes the migrated layout hard to be recognized and verified by designers. In nanometer processes, via has been one of important factors to cause manufacturing defect. For this critical problem, foundries suggested IC designers using redundant via to connect metal wires on different layers. This thesis based on the previous work. Additionally, the space in specific area was preserved for redundant contacts and vias. The migration flow contains Y-direction linear programming base redundant contact and via aware migration and X-direction constraint graph base redundant contact aware migration. Experimental results show that about 40% improvement of failure rate for benchmark circuits implemented by our cell library is achieved without extra cost in total cell area, on the other hand the timing difference of the our cells and the cells without considering redundant contact and via is at most 2%. On the other hand, the number of redundant contacts can be traded of against cell area under the proposed cost.