以固定式暫存器分配方法為基礎之低功耗低面積資料格式轉換器設計

Abstract

在本篇論文之中，我們針對資料格式轉換器(DFC)的架構設計提出了一項低功率低面積的暫存器分配之演算法。我們所提出的固定式暫存器分配方法不只是具有最小的功率消耗與暫存器資料寫入次數，而且在DFC的設計中使用的面積也不會太大。從16位元的3x3, 4x4, 16x16的矩陣轉置器與IIR filter的DFC測試項目中，在0.18um CMOS製程上與SSRA的方法比較來看，功率消耗分別減少了27.4%, 45.3%, 50.2 %以及25.7%，而晶片面積分別減少了44.6%, 51%, 53.9%以及38%；另外從16位元的1-D DWT, Zigzag scanner, 4x4 par-transposer的2-D DFC測試項目中，在0.18um CMOS製程上與SSRA的方法比較來看，功率消耗分別減少了5.3%, 13.6% 以及16.1 %，而晶片面積分別減少了28.9%, 33.6% 以及 26.4%，所提出的固定式暫存器分配方法有著最低的功率消耗與較低的晶片面積在這幾種方法之中。最後利用SRA方法設計WiMAX傳輸端之的Interleaver，以驗證在本文所提出的想法。

In this thesis, we explore one low power and area efficient register allocation algorithm for data format converter (DFC) architecture designs. The proposed static register allocation (SRA) approach not only minimizes the power and number of register transitions, but also achieves a comparable area cost for DFC designs. From the implementation results of 16-bit 3x3, 4x4, 16x16 transposer, and IIR filter benchmarks using 1-D SRA, the power consumption can be alleviated by 27.4%, 45.3%, 50.2% and 25.7% respectively, compared with the SSRA design in 0.18 um CMOS process. The core area reduction by 44.6%, 51%, 53.9% and 38% can be achieved for the same cases. From the implementation results of 16-bit 1-D DWT, Zigzag scanner and 4x4 par-transposer benchmarks using 2-D SRA, the power consumption can be alleviated by 5.3%, 13.6% and 16.1%, respectively, compared with the SSRA design in 0.18 um CMOS process. The core area reduction by 28.9%, 33.6% and 26.4% can be achieved for the same cases. Thus, the proposed SRA-based design has lowest power consumption and cost effective among the several approaches. Finally, we implement the interleaver using SRA for WiMAX system.