類比電路中之n型金氧半導體場效電晶體元件汲極電流低頻雜訊之探討

Abstract

CMOS元件技術具有較低成本、高製程整合度、以及低功率的優點；但在類比電路的應用中，卻有一主要缺點，及其汲極電流低頻雜訊過大。為了將金氧半導體場效電晶體成功的運用在類比電路中，元件設計者必須徹底了解低頻雜訊的物理來源。 首先，吾人將先針對金氧半導體場效電晶體元件中汲極電流低頻雜訊的熱載子效應作徹底研究。吾人發現，因熱載子效應的影響，在元件氧化層中會行成局部的氧化層電核累積，此種不均勻的氧化層電核分布，將會造成通道臨界電壓分布的不均勻，此即為造成雜訊衰減的主要原因。除此之外，吾人也提供一簡單之兩區域模型使讀者更加了解我們所提的現象。 接下來，吾人將探討在0.13mm CMOS製程中，pocket implantation 製程對於金氧半導體場效電晶體汲極電流低頻雜訊之影響。吾人研究結果顯示，pocket implantation製程將會嚴重的衰減低頻雜訊特性，其原因如下，因為pocket implantation的影響，在元件通道中的臨界電壓之分布已為不均勻。吾人同時提供一兩區域低頻雜訊模型來描述此pocket implantation對於元件低頻雜訊的影響。在我們提供的模型中，所有參數均由元件量測資料中萃取出來，無任何可隨意調整之參數。此外，根據此模型模擬之結果與量測資料非常吻合。基於相同的理論基礎，吾人可以利用元件低頻雜訊的量測，萃取特殊ONO記憶體元件介電層中之載子儲存分布，此分布之資料為記憶體電路設計之重要資訊。 再者，吾人同時使用2-D元件模擬軟體 (MEDICI) 來驗證不均勻的元件通道臨界電壓分布對於元件低頻雜訊之影響。吾人在模擬時，利用改變基底電壓與pocket doping profile，來驗證通道載子分布不均勻時，對低頻雜訊之影響，其結果與吾人所提之兩區域低頻雜訊模型預測結果相同。 最後，吾人探討在超薄氧化層 (15Å) 金氧半導體場效電晶體元件中低頻雜訊的物理來源。根據研究結果，吾人提出一種由valence band tunneling所導致之低頻雜訊來源。在strong inversion的情形下，valence band中的電子將穿透超薄氧化層，並在valence band中留下電洞，如此一來，造成電子電洞的不平衡，並導致電子與電洞的quasi Fermi-level分開。所以，在超薄氧化層元件中之低頻雜訊來源為電子與電洞在interface traps中recombination所產生之generation/recombination雜訊。我們同時分析time-domain中的雜訊，即所謂random telegraph signal，其結果與我們所提出之低頻雜訊來源相符合。

CMOS technology is superior in its low cost, high integration, and low power; nevertheless, there is a major drawback in analog applications. The MOSFETs are so noisy although so called “analog low noise” fabrication process is used. Apart from white thermal noise, MOSFETs are notorious for flicker noise in the low frequency range. So as to improve the MOS circuit’s dynamic range and get better circuit performance, a device designer has to understand the physical origin of flicker noise. First of all, the hot carrier degradation mechanisms of drain current flicker noise in analog n-MOSFETs are investigated. From our observation, the non-uniform threshold voltage distribution generated by local oxide charges after stressing could give rise to series flicker noise degradation. A simple two-region flicker noise model can be used to give better understanding of this behavior. Next, pocket implantation effect on drain current flicker noise in 0.13mm CMOS process based high performance analog n-MOSFETs is investigated. Our result shows that pocket implantation will significantly degrade device low-frequency noise primarily because of non-uniform threshold voltage distribution along the channel. An analytical two-region flicker noise model to account for a pocket doping effect is proposed. In our model, the local threshold voltage and the width of the pocket implant region are extracted from measured reverse short channel effect and the oxide trap density is extracted from a long-channel device. Good agreement between our model and measurement result is obtained without other fitting parameters. In addition, non-uniform threshold voltage distribution along the channel resulting from CHE programming in special ONO charge storage cells would increase drain current flicker noise. Based on the same concept of two-region model, one can extract programming charge distribution in NROM memory devices from noise measurement. Then, we use a two-dimensional device simulator, MEDICI, to simulate the effect of channel carrier distribution variation on flicker noise. The substrate bias and pocket doping profile is changed to verify the relation between channel carrier distribution and drain current flicker noise. The results show good agreement with the analytical model prediction. Finally, low frequency flicker noise in analog n-MOSFETs with 15Å gate oxide is investigated. A new noise generation mechanism resulting from valence band electron tunneling is proposed. In strong inversion condition, valence-band electron tunneling from Si substrate to poly-gate takes place and results in the splitting of electron and hole quasi Fermi-levels in the channel. The excess low frequency noise is attributed to electron and hole recombination at interface traps between the two quasi Fermi-levels. Random telegraph signal due to capture of channel electrons and holes is characterized in a small area device to support our model.