低介電係數材料應用於銅導線內連接製程之可靠度研究

Abstract

本論文針對於銅製程內連線之低介電係數介電材料(Low-k Dielectrics) 之可靠度特性，提供一個完整的可靠度預測模型與評估，包含可靠度與介電係數 (k) 的相關性、銅導線線寬變異 (Line Edge Roughness, LER) 對介電材料可靠度的影響，以及介電材料生命期之電場加速模型研究。

隨著半導體製程的持續微縮，為了降低銅內連線製程的 RC delay，使用較低電阻係數的銅導線已被廣泛應用於 0.13 微米以下的製程。然而，為了更進一步降低 RC delay 於尺寸更微小之製程，降低介電材料的 k 值已經成為必要之手段，實驗數據顯示，若介電材質 k 值愈低，其絕緣可靠性愈差 (生命期降低)，但其基本物理失效機制及可靠性預測模型則尚未被清楚瞭解。因此，建立一低介電材料可靠度生命期與介電係數 (k 值) 關係的定量預測模型對未來低介電材料的選擇已成為一重要的課題。除了 k 值之外，由製程微縮引起的銅導線線寬變異亦會對可靠性造成顯著的影響，原因為奈米線寬等級之銅線導尺寸不易控制，在微影、蝕刻、化學機械研磨各項製程上的變異性 (Variability) 均會導致銅線導線寬的變異，並會嚴重降低在介電材料在加速條件之可靠性壽命。亦即，微小尺寸介電材料可靠性之生命期同時為線寬幾何尺寸及低介電係數材料特性的函數，如何正確分析低介電材料之可靠性在本論文有詳細討論。

在材料與低介電係數(k)之相關性方面，本論文探討孔洞 (pore) 在介電材料失效機制上所扮演的角色, 以及孔洞的添加量對介電材料的可靠度之影響。孔洞添加於介電材料中可有效降低 k值，並已在工業界廣泛的應用於 65 奈米以下之銅導線內連線製程之中，孔洞由於 k 值 (k=1) 小於 SiOC 介電材料 (k~3.6)，因此使得孔洞成為一局部高電場區域，此局部高電場會增加電流在介電材料內的傳導能力，進而加速介電材料的崩潰失效 (dielectric breakdown failures)。因此，較高的孔洞密度 (porosity)會導致較低的可靠性生命期，但其基本失效機制卻未改變。本論文延伸應用已廣泛使用於二氧化矽閘極氧化層崩潰之統計模型(percolation model)，並考慮孔洞在此模型內扮演的角色等效於縮短介電層厚度，提出一應用於低介電材質可靠度預測的統計模型，此模型已經由實驗結果所驗證，並可用於未來更低 k 值材料 (k<2.5) 之可靠性預測。

隨著IC製程的微縮，銅導線線寬的控制已成為微影及蝕刻製程之嚴峻挑戰，銅導線線寬的微小變異已無法忽略，其原因是此線寬變異會使得銅導線之間之介電層厚度不再為定值，使得介電層內之電場分佈不均勻，造成局部銅導線週圍有高電場作用於介電料材之中並降低介電料材之可靠度。本論文從理論出發，首先根據銅導線線寬變異性建立一線寬模型，進而估算介電材料的厚度分佈。結合此介電材料厚度分佈與生命期電場加速模型，我們計算出介電材料在高電場加速條件下會失效在最小厚度處。然而，在低電場產品使用條件下，介電材料卻會失效在平均厚度處，材料本質特性是限制低電場介電材命特期之主要機制。因此，如何在加速條件生命期實驗數據中取得介電材料本質特性，需考慮對奈米尺寸導線變異性對生命期的影響並加以修正，方能得到對介電材料可靠性的正確評估。

除了 k 值與線寬變異之外，介電材料生命期的電場加速模型(Field Acceleration Model) 對可靠性的預估影響甚鉅，使用電場加速實驗的目的在於可利用在有限的時間內取得之可靠性實驗數據，藉由加速模型便可推估出產品在低電場使用條件下之生命期。然而，實務上的困難是，在高電場加速壽命實驗中，多數的電場加速模型皆能描述其生命期數據，但是不同的加速模型推估出的低電場生命期卻有數個數量級的差別，因此仍無法對介電材料的可靠性做出一準確的評估。電場加速模型通常由其失效之物理機制所決定，但是目前對低介電材料失效的物理機制仍未有定論，目前有許多不同的電場加速模型仍在討論之中，其困難之處在於模型的驗證需仰賴低電場條件下的實驗數據，但此數據之取得需花費極長的時間(數個月至數年)，因此不易執行。再者，低介電材料之可靠性易受許多外在製程因素所影響，例如介電材料會因銅離子污染、吸附水氣、銅線線寬變異、及電漿蝕刻破壞等因素而降低其可靠性，進而無法正確評估介電材料之正確電場加速模型。在本論文中，我們利用線寬尺寸變異在不同電場測試條件下，其可靠性失效分佈(韋伯分佈)之形狀參數 (β) 之變化趨勢來驗證正確的電場加速模型。從實驗數據中我們觀察到 β 會隨著加速電場下降會增加，此行為符合 E或√E 模型之預估，但不符合power law 及1/E 模型之行為，E及√E模型之差異在此論文中仍無法有效分辨，但此二模型之確立已有效降低可靠性預估來自於不同模型之估計誤差。

結合孔洞及線寬尺寸變異對可靠性的瞭解，我們建立一完整的低介電係數材料可靠性模型評估材料的本質特性，進而可用於預估低介質材料在微縮進程中之可靠性衰減速度。根據本研究之實驗數據，本論文提出之低介電係數材料可靠性模型可正確描述可靠性生命期與 k 值之關係，並指出當 k 值小於 2.3時，其生命期會驟降數個數量級之多，原因是由於孔洞密度過高(大於30%)，孔洞間會彼此連結並形成一高電場通道並縮短崩潰路徑 (percolation path) 進而造成介電材料崩潰，此一特性為孔洞分佈之統計特性並與製程及電場加速模型無關，此為一基本之材料特性限制，此項研究可用於未來低介電係數材料選擇上之參考。

This dissertation presents the modeling and characterization of low-k dielectric reliability of advanced Cu dual damascene interconnects. As the semiconductor integrated circuit continues shrink, the RC delay of interconnect has to decrease with the technology scaling for the need of speed and power consumption of advanced circuits. Since copper wire has been implemented to reduce R from 0.13um technology node, the major approach to further reduce RC delay is to use low-k dielectric material for advanced Cu interconnects. However, the reliability of low-k dielectric becomes a serious issue with the technology scaling. Both dielectric material scaling (lower dielectric constant) and interconnect geometrical size scaling will degrade the dielectric reliability.

In this thesis, we investigated both the dielectric constant (k) and geometrical size dependence on the dielectric reliability. We develop a statistical model to accurately describe low-k failure distribution as a function of dielectric constant k and Cu line edge roughness (LER). In addition to the failure distribution modeling, we verified the field dependence of low-k breakdown by characterizing the geometrical variation effect on failure distributions. We show that both E- and □E-model are reasonable to describe the field dependence of low-k failures.

It is well known that the low-k dielectric reliability degrade with the decreasing k-value because of the weakened dielectric breakdown strength. However, the fundamental understanding of this k-dependence is not clear in the semiconductor industry and there is no quantitative model to predict the dielectric reliability of Cu interconnects. In this thesis, we explained pore is acting as the local field enhancement region and will enhance the current conduction inside the dielectrics. The increasing porosity (decreasing k) will shorten the breakdown path and degrade low-k reliability based on the percolation theory.

In addition to the k-scaling impact on low-k reliability, the Cu conductor line edge roughness (LER) has been an important issue from the reliability perspective. LER of Cu will cause a non-uniform dielectric thickness distribution between Cu wires and give a local high electric field region at the place of the small dielectric thickness and dominate dielectric failure time. We theoretically calculated this LER effect on dielectric failure time and determine the failure thickness as a function of test voltages. We show that the failure thickness occurs approximately at the place of minimum dielectric thickness under high voltage acceleration test conditions, while will shift to the nominal thickness at low-voltage use conditions because of the decreasing field acceleration effect. This analysis indicates that LER will dominate the failure distribution at high voltage test conditions but the intrinsic material property is relevant at low voltage use conditions. In this thesis, we demonstrate the de-convolution of LER and intrinsic low-k material properties from the acceleration failure distributions. We also show the shift in failure thickness will also introduce systematic errors for field acceleration model characterization if the stress electric field does not take this effect into account. We also analyzed the LER effect on failure distribution shape as a function of applied test voltages for various field dependence model of failures and concluded that E- or □E-model is reasonable to describe the field dependence of dielectric failures.

Finally, combining the LER and porosity effect into a percolation theory, we show that Cu/low-k damascene interconnect is capable of approaching intrinsic performance of low-k dielectrics the with the process optimization. We model the intrinsic low-k reliability capability as a function of k. Our model show the low-k dielectric failure time will drop rapidly when k<2.3 (porosity > 30%) because the high density pores will connect to each other and form a high current path to enhance breakdown. This is the statistical nature for porous low-k dielectric breakdown and can be viewed as a fundamental limitation of porous low-k dielectrics.