低介電常數材料在多層導體連線系統上之製程整合研究

Abstract

當元件尺寸進入奈米領域 (<100 nm)時，訊號傳輸的電阻-電容時間延遲 (RC delay time)是現今多層金屬連線製程技術急需解決的問題。為了克服這一個問題，在內層金屬連線結構中使用金屬銅導線與低介電常數材料是一個不錯的方法。然而當低介電常數材料與銅導線製程整合時，將面臨到不同於昔知製程技術的挑戰。所以本論文將研究四種極具潛力的低介電常數材料: Methylsilsesquiazane (MSZ)，Porous Polysilazane (PPSZ)，Hydrogen Silsesquioxane (HSQ)，以及Porous Organosilicate Glass (POSG)，並對其所遇到之製程整合問題提出相關的解決方法。 在傳統的多層導體連線微影製程中，去除光阻的步驟是無法避免的。而在去除光阻的過程中，氧電漿灰化是主要的製程方式。本論文發現氧電漿會造成低介電常數材料介電特性的劣化，而且實驗結果顯示多孔性的低介電常數材料比一般的低介電常數材料更容易被氧電漿破壞。這是因為多孔性的低介電常數材料有較大的表面面積，所以氧電漿容易擴散入材料中，並與材料中的官能基(如甲基鍵等)反應形成Si-OH鍵結，而這些極性鍵結很容易吸附外界的水氣，進而造成介電特性的劣化。為了防止低介電常數材料在光阻去除過程中受到傷害，本文採用在氧電漿處理前利用H2與NH3電漿處理，使其在低介電常數材料上形成鈍化層以防止後續氧電漿的破壞。實驗結果顯示此方法是可行的。另外，對於低介電常數材料在光阻處理過程中所產生的Si-OH鍵結，也可以用trimethylchlorosilane (TMCS)與hexamethyldisilazane (HMDS)的化學處理方式置換成Si-O-SiMe3的疏水性原子團，並有效的恢復被氧電漿所破壞的介電特性。 為了能夠進一步將銅導線與低介電常數材料整合在一起，鑲崁式的銅導線結構是目前極為可行的製程方式。而在此製程中，化學機械磨製程(CMP)將扮演非常重要的角色。但是隨著晶片(chip)的功能越來越強大，其電路佈局的複雜性與積集度也日益增加，使得CMP的終點偵測日益困難，因此本論文將研究國家奈米實驗室(NDL)所提供的TaN與Cu研磨液在CMP製程中對低介電常數材料介電特性的影響。實驗結果顯示此兩種研磨液並不會對MSZ與PPSZ材料的介電特性有任何的影響，而且其對這兩種材料的研磨速度也比TaN與Cu金屬低很多。因此利用此兩種低介電常數材料於銅導線製程中可以使終點偵測比較容易，且其介電特性在此CMP製程中不會受到影響。另外，在電性可靠度分析上，本研究也發現MSZ與PPSZ材料與銅金屬有良好的可靠度，因此MSZ與PPSZ材料在鑲崁式銅導線製程的應用上是很有潛力的。 由於金屬沉積前介電層(PMD)的低溫化與平坦化的要求日益重要，使得低介電常數材料的CMP平坦化製程有探討的必要性。本論文發現利用傳統的矽酸鹽類研磨液(SS-25)不能對MSZ或PPSZ產生高的研磨率，因此吾人提出利用氧電漿處理的方法來增加含有甲基的MSZ與PPSZ薄膜之研磨率。氧電漿可以在MSZ或PPSZ薄膜表面形成一親水層進而提高SS-25研磨液對此低介電常數材料的研磨率，而且一旦此親水層被磨除後，此低介電常數材料就會被恢復到原本的低介電特性。 此外，為了避免去除光阻製程對低介電常數材料的傷害，以及符合下一世代微影製程的要求，本論文亦提出一種利用電子束(e-beam)對低介電常數材料直接圖形化的技術。此技術是利用電子束的能量使低介電常數材料固化，然後再利用適當的溶劑進行圖形的顯影以得到想要的電路圖案。研究發現此技術確實可以運用於低介電常數材料的圖形化，但需要在圖形化製程後多一道熱退火的製程才能得到理想的低介電常數材料特性。 在對多孔性POSG低介電常數材料進行e-beam直接圖形化的實驗中，吾人發現此材料經過電子束照射，顯影製程與後續熱退火製程後，其介電常數竟然比傳統熱爐管固化的POSG薄膜要來的低。經過實驗的分析得知，可能的原因是由於電子束照射只能使POSG材料產生局部的網路連結(crosslink)，所以在顯影過程中部分未連結的聚合單體會被顯影液所帶走而留下孔洞，因此經過熱退火製程後其薄膜的孔隙度會比傳統的熱爐管固化材料還要來的高，導致出現更低的介電常數值。而在漏電傳導機制的研究中，發現電子束的照射會使POSG材料的漏電機制由原本熱爐管固化POSG的Schottky emission傳導機制轉變成Space-charge-limited current的傳導機制。

Although the dimension of device has shrunk into nano technology node, the RC delay of inter-metal interconnection has still been the urgent issue needed to be resolved so far. In order to overcome this problem, the introduction of low-dielectric-constant (low-k) material for inter-metal interconnection can effectively reduce the RC delay. However, it is necessary to estimate the compatibility of low-k materials on semiconductor process during the integration of Cu and low-k materials. In this dissertation, four types of low-k materials are investigated: Methylsilsesquiazane (MSZ), Porous Polysilazane (PPSZ), Hydrogen Silsesquioxane (HSQ), and Porous Organosilicate Glass (POSG). In the traditional lithography process for integrated circuit manufacture, photoresist removal step is an inevitable process. O2 plasma ashing is the main method to remove the photoresist during photoresist (PR) stripping process. It was found that the oxygen plasma will degrade the dielectric properties of low-k material. We have found that the porous low-k materials are more easily damaged by O2 plasma than that of dense low-k materials. This reason is that the porous low-k materials have larger exposed surface area than that of dense low-k materials. As a result, the oxygen radical can easily diffuse into material and react with the functional group, such as methyl bonding, which is converted to Si-OH bonds. These polar chemical bonding can lead to moisture uptake under atmosphere, resulting in dielectric degradation. In order to prevent the low-k materials from O2 plasma damage during photoresist stripping process, H2 and NH3 plasma treatments were applied to low-k materials before PR stripping process. These plasma treatments can effectively form a passivation layer on the surface of low-k materials and protect the low-k materials from O2 plasma damage. Besides, the Si-OH formed from O2 plasma ashing process can also be eliminated by trimethylchlorosilane (TMCS) and hexamethyldisilazane (HMDS) post-treatment. These chemical treatment can change the hydrophilic Si-OH into hydrophobic Si-O-Si(CH3)3 bonds so that the dielectric characteristics of low-k materials can be recovered. In order to integrate the Cu and low-k materials into multilevel interconnection, the Cu damascene structure has been accepted to be a promising architecture up to now. In this process, the chemical mechanical polishing (CMP) technology will impersonate a critical role. However, with the functionality of chip is more powerful, the complexity and density of circuit layout are increased more significantly. This will cause the end point detection of CMP process more difficultly. Therefore, there are two slurries (TaN and Cu slurries), which is provided by national nano device laboratory (NDL), used to investigate the impact of CMP process on dielectric properties of low-k materials. It was found that these two slurries can not influence the dielectric properties of MSZ and PPSZ during CMP processes. Moreover, the selectivity of Cu or TaN with respect to MSZ and PPSZ films is high as polished by Cu or TaN slurries. Therefore, manufacturing Cu interconnect using the two low-k materials can make the end point detection easily and do not influence the dielectric properties during CMP processes. In addition, it was found that the electrical reliability of Cu and these two materials can be remained under reliability test. Therefore, the application of MSZ and PPSZ for Cu damascene structure has a lot of potential. In virtue of the requirement of low thermal budget and high planarization for pre-metal dielectric (PMD) is gradually significant in future, it is necessary to investigate the CMP of low-k materials in this study. The experimental results represent that the high polishing rate of MSZ or PPSZ can not be obtained by using commercial silica-based SS-25 slurry. Therefore, O2 plasma pretreatment on low-k materials is proposed to improve the polishing rate of low-k materials. The O2 plasma can react with MSZ or PPSZ to form a hydrophilic layer, which will raise the polishing rate of methyl contained MSZ or PPSZ films with SS-25 slurry. Moreover, the dielectric properties of these low-k materials can be maintained as the hydrophilic layer was polished away. In addition, a novel electron beam (e-beam) direct patterning technology is proposed so as to avoid the damage during photoresist removal process. The e-beam energy can provide energy to cure the low-k materials from mono-polymer structure into network structure. Then, the uncured region of low-k materials can be dissolved by suitable developer. After development process, the desirable pattern can be obtained by this technology. But an additional thermal annealing is needed to achieve the required low-k dielectric properties. During the experiment of e-beam direct patterning on porous POSG film, it was found that the dielectric constant of e-beam exposed POSG after development and thermal annealing processes is lower than that of traditional furnace cured one. The possible reason is that the e-beam exposure can only partially crosslink the POSG films. Once the e-beam exposed POSG is subjected to developer, the uncrosslinked polymer of POSG will be taken away, resulting in the pore in POSG films. After the thermal annealing process, the porosity of film will be higher than that of traditional furnace cured one. In addition, the leakage current behavior of e-beam exposed POSG film is investigated. After e-beam exposure, there are many charge trapping sites remained in POSG films, which will cause local potential barrier height and affect the carriers transport in POSG film. Electrical analyses reveal that the behavior of leakage conduction mechanism of POSG will be from Schottky emission transferred into Space-Charge-Limited Current (SCLC).