標題: 低介電常數材料甲基矽酸鹽類之製程整合研究
Low dielectric constant material methylsilsesquiane (MSZ) for interconnect application
作者: 彭若慈
Jo-Tzu Peng
陳家富
張鼎張
Chia-Fu Chen
Ting-Chang Chang
材料科學與工程學系
關鍵字: 低介電常數;光阻灰化;化學機械研磨;low-k;dielectric;CMP
公開日期: 2001
摘要: 本論文研究一低介電常數材料MSZ(Methylsilsesquiazane)薄膜在積體電路(IC)製程整合的技術。低介電常數材料MSZ (Methylsilsesquiazane)是屬於一種有機類的高分子矽酸鹽聚合物,類似Methylsilsesquixane (MSQ),也是一種旋塗式塗佈的低介電常數材質。由於在積體電路的製造技術中,光阻的去除,常是利用氧電漿處理的方式來將光阻中的碳氫成份分解,達到光阻灰化的目的。實驗結果發現,當低介電常數材料MSZ經過光阻去除的製程步驟後,low-k薄膜的介電特性將會劣化。這是因為在去光阻時,其官能基遭受破壞之故。因而low-k薄膜吸收外界水氣,進而造成薄膜介電性質的劣化。在本論文中,我們利用電漿製程處理low-k薄膜,藉由適當之事前預防處理,形成一層薄的鈍化層,以防止low-k薄膜在去光阻過程中,遭受氧電漿灰化及化學濕式剝除液的損害。另一方面,也可將製程中已遭損害之薄膜,經由事後的補救製程,利用化學溶液的取代反應來修復其損害之部份,藉以恢復其low-k薄膜原本的特性。實驗結果發現,經後續處理後之low-k薄膜,即使經過光阻去除步驟,其漏電流及介電常數仍可維持於一個極低的狀態。因此,不論電漿或是化學方式的處理皆可避免low-k薄膜在光阻去除過程中遭受損害。 另外在多層導體連線中,平坦化是一個非常關鍵的步驟,而化學機械研磨(CMP)製程是目前公認達到全面性平坦化最可行之方法,因此本論文中,經過化學機械研磨後之MSZ薄膜,其漏電流和介電常數會因為研磨過程的破壞而少許的增加,但並無很明顯的劣化。除此之外,由於研磨速率太慢,因而提出利用氧電漿的前處理來使薄膜表面成親水性,進而增加研磨速率,結果研磨速率的確增加便為兩倍,並且並無劣化之情形造成。因此在新世代積體電路製程中,MSZ應具發展潛力。
In this thesis, we will investigate the integration of low-permittivity (low-k) Methylsilsesquiazane on interconnect technology. Methylsilsesquiazane (MSZ) is one class of organic polymers, which has a similar structure as Methylsilsesquixone (MSQ) and exhibits a relatively low dielectric constant (k=2.5~2.6) as compared to SiO2 (k=4.0). It is intrinsically hydrophobic, has reasonable mechanical hardness, and possesses exceptional thermal and dimensional stability (in excess of 550oC). For these reason, MSZ represents an excellent candidate for the application on the multilevel interconnects technology. In the present IC manufacturing processes, photoresist stripping is commonly implemented with O2 plasma ashing. Dielectric properties of MSZ film, however, could be degraded during photoresist removal. To mitigate the issue, gas plasma pre-treatment (H2 and NH3 plasma) and chemical solution (trimethylchlorosilane TMCS and hexamethyldisilazane HMDS) post-treatments were applied to the MSZ film against O2-plasma impact. Material and electrical analyses were also used extensively in this work to explain their capabilities improvements. On the other hand, surface planarization is a key technology during the manufactures of multilevel interconnects. Chemical mechanical planarization (CMP) process is satisfactory for the requirement of global planarization technology. As a result, a novel CMP process for the low-k interlayer has been proposed to enhance the performance of IC. The influence of CMP processes with various slurries on the MSZ film was first investigated. Simultaneously, a novel oxygen plasma treatment technique for the CMP process of the low-k MSZ has been proposed because the removal rate is still too low with SS-25 slurry and the additive TMAH. We also investigated the impact od MSZ after CMP process with oxygen plasma pre-treatment on the dielectrics. Material and electrical analyses were used to interpret these impacts. Finally, we have also explored the reliability issue related to copper penetration in low-k MSZ film.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT900159005
http://hdl.handle.net/11536/68253
顯示於類別:畢業論文