運用於射頻系統封裝應用之異質整合技術開發

Abstract

在不久後的將來，由於材料特性與元件結構的自然限制，矽基互補式金屬氧化物半導體(CMOS)技術的持續微小化將不再遵守摩爾定律(Moore’s Law)之預測而達到其終點。例如，當通道長度低於9奈米時，金氧半場效電晶體(MOSFET)將表現出較大的漏電流從而導致功率消耗之增加。相較於CMOS技術的微小化，在微電子系統的發展中，一個新興的技術趨勢在於實現超越摩爾定律(More than Moore)之目標，對於未來微電子系統的效能提升，主要將集中於系統整合之技術發展而非電晶體密度之增加來創造高附加價值與功能多樣化之微電子系統。因此，系統封裝(SOP)將成為一個非常重要的技術發展方向來整合CMOS與non-CMOS元件，例如無線被動元件、感測器與制動器、微流道…等，於一個單一封裝體之中。此篇博士論文之目標即為開發應用於下一世代高效能、低成本智慧型系統製造的射頻系統封裝(RF SOP)之關鍵技術發展。憑藉著系統封裝的優點可進一步將現有組裝了大量元件的龐大電路板縮小在一個微型封裝基板中，此優點伴隨著一個技術挑戰，其技術難度在於如何整合所有的CMOS晶片於封裝基板之上並且具有低損耗與低寄生效應的連接特性，特別是在射頻系統整合方面，為了克服這個困境，在此論文中首先提出用於異質晶片整合(Heterogeneous chip integration)之金-金熱壓接合(Au-Au thermocompressive bonding)技術,此技術可以提供一個低損耗的連接而不需要在電性轉接結構上採用複雜的結構設計或額外的阻抗匹配，從DC到50GHz頻率範圍可具有低於-15dB的返回損失及-1.8dB的插入損失。為了展現此連接技術在射頻微機電異質晶片整合的可行性，ㄧ個低功率射頻低雜訊放大器(Low noise amplifier)藉由整合TSMC 0.18-μm RF CMOS晶片與製作有高品質因子微機電式電感(high-Q MEMS Inductor)的矽載具(Si carrier)被提出來，此連接技術與矽載具系統封裝應用方案也可以使用在其他微電子封裝應用，例如：軟性電子，光電，微機電系統…等。 在此論文中，軟性電子應用(Flexible electronics)是另一個研究主題之概念展示。以軟性微電子整合為例，首先提出了先進SU-8微加工製程來展現嵌入元件在軟性基板的可行性，利用此製程可使製作微機電串聯式切換器(MEMS serial switch)之製程溫度低於135□C。提出之SU-8微機電切換器為靜電力驅動之兩端固定SU-8樑結構，高頻特性方面在12GHz可提供-28.2dB之高隔離度，若製作於100□∙cm之矽晶圓之上由於降低了基板損失則預期具有低於-0.75dB之插入損失。此外，與先前矽基射頻系統封裝概念相同，吾人發展並提出一個低成本晶圓級軟性微系統整合技術來實現軟性射頻系統封裝，此技術合併先前開發之無凸塊射頻系統封裝連接方案與特殊的表面清潔製程來達成接合溫度低於200°C之CMOS晶片組裝於SU-8/PDMS有機基板之上。射頻轉接結構在有機基板上同樣展現低損耗的特性，在40GHz有大約-15dB返回損失與-0.8dB插入損失。此外，相同的整合製程被利用來整合生醫矽探針與SU-8軟性帶狀排線以提供可靠的信號傳輸至人體外部之讀取設備。同時，利用金化學惰性的優點，晶圓級犧牲層釋放製程也被提出來實現未來低成本批次製造之軟性微系統。 除了組裝晶片於封裝基材之上，在射頻系統封裝的進展上，發展高效能嵌入式被動元件是非常關鍵的，因此，在論文的最後部分，吾人研究並提出整合鐵磁性鐵芯之晶片式螺旋電感，晶片式電感被大量使用於射頻積體電路(RFIC)的設計上，然而，電感通常佔據大部分矽晶片之面積且無法隨著CMOS技術的進步而縮小，同時，電感的性能會受到如導體結構的電阻損耗(resistive loss)與矽基板損耗(substrate loss)等自然限制，因此吾人提出合併磁性奈米複合材料，包括鎳-磷-陽極氧化鋁(Ni-P-AAO)與鎳鐵-陽極氧化鋁(NiFe-AAO)材料，來作為晶片式電感之感應鐵芯以提升電感值，使用NiFe-AAO奈米複合磁性鐵芯之螺旋電感在GHz頻率可提升約25%之電感值並且沒有大幅的品質因子降低，本論文將提出相關磁性奈米複合薄膜之詳細實驗流程與奈米複合電感之整合製程與量測討論。

In the near future, the continuous downscaling of Si-based CMOS technology will not follow the Moore’s Law and would reach its endpoint owing to the nature limitation of the material property and device structure. For instance, MOSFET channel lengths below 9 nm will exhibit higher leakage currents leading to increased power consumption. Instead of the CMOS scaling, an emerging technology trend in the development of microelectronics system is aimed to realize the goal of “More than Moore”, indicating the future performance improvement of an microelectronic system would mainly focus on the technology of system integration rather than transistor density increase for creating high value and functional diversification of microelectronics systems. Thus, the integration of CMOS and non-CMOS based components, such as wireless passive components, sensors and actuators and microfluidic channel and so on, within a single package, i.e. system-on-package (SOP), would become an important technology development direction. The objective of the dissertation is to develop the key technologies of radio frequency SOP for the next generation high performance and low cost smart system fabrication. The virtue of SOP is aimed to further shrink a bulky circuit board assembled with components into a miniature packaging substrate. The virtue would come with a technical challenge which is the difficulty in the integration of a packaging substrate with all CMOS chips with low loss and low parasitic of interconnections, especially in RF system integration. To overcome this predicament, an interconnecting technology using an Au–Au thermocompressive bond is presented first in the dissertation for the heterogeneous chip integration. This technology can provide a low loss interconnection which is less than -15 dB return loss and -1.8 dB insertion loss up to 50 GHz without implementing complex structure designs and extra impedance matching networks in the electrical transition. A low-power RF low-noise amplifier by integrating a TSMC 0.18-μm RF CMOS chip with a silicon carrier substrate, where high Q MEMS inductors are fabricated, is proposed to demonstrate the feasibility of the interconnecting technology for RF MEMS heterogeneous chip integration. Such an interconnecting and the Si carrier SOP application schemes can be also applied to the other microsystem packaging applications like flexible electronics, optoelectronics, MEMS and so on. In the dissertation, flexible electronic application is another subject for the concept demonstration. For the case of flexible microsystem integration, a novel SU-8 micromachining process for MEMS series switch fabrication with processing temperature lower than 135□C is presented first to show the feasibility to embed devices in a flexible substrate. The proposed SU-8 MEMS switch is designed with a clamped–clamped SU-8 beam structure driven by electrostatic force. The switch can exhibit better than −28.2 dB isolation up to 12 GHz and expect to have −0.75 dB insertion loss as long as the substrate resistivity is increased up to 100 □∙cm resulting in lower substrate loss. Then, a low-cost wafer-level flexible microsystem integration technology is developed and presented for the ultimate realization of flexible RF SOP same concept as the prior Si-based RF SOP. The technology combines the previously developed bumpless RFSOP interconnection scheme with a special surface cleaning process to assemble a CMOS chip with an organic substrate (SU-8/PDMS) that the bonding temperature less than 200°C. The RF transition on the organic substrate also provides a low loss performance about -15dB return loss and -0.8dB insertion loss at 40GHz. In addition, the same integration process is utilized to integrate the biomedical Si probe with an SU-8 flexible ribbon cable for providing a reliable signal transmission to the instrument reader outside human body. Meanwhile, by taking advantage of chemical inertia of Au, a wafer-level sacrificial release process is also proposed and performed for future low-cost batch fabrication of flexible microsystem. In addition to the assembly of chips onto a packaging substrate, developing high performance embedded passive components is very critical in the advancement of RF SOP technology. Thus, in the last part of the dissertation, on-chip spiral inductor with ferromagnetic core is developed, investigated, and presented. On-chip inductors have been extensively used in the design of Radio Frequency Integrated Circuits (RFICs). It, however, occupies a large silicon chip area which cannot be scaled with the advancement of CMOS technology. Meanwhile, the performance of the inductor suffers with its nature limitation owing to resistive loss of its conducting structure and silicon substrate loss. An inductance enhancement scheme is then proposed to incorporate magnetic nanocomposite materials including Ni-P-AAO and NiFe-AAO with on-chip inductors as the inductive cores. The spiral inductor using a NiFe-AAO nanocomposite magnetic core can have more than 25% inductance enhancement without tremendous Q degradation to GHz range. The detail experimental procedures of synthesis and characterization of magnetic nanocomposite films, the integration process of nanocomposite inductors, and the related measurements and discussions are all presented in this dissertation.