在實體設計階段改善設計品質/診斷能力之方法

Abstract

在今日晶片設計流程的每個設計階段中，實體設計階段（physical design）將電路設計從閘層級電路（gate-level netlist）實做成為幾何佈局（geometric layout）的關鍵性階段。平面規劃（floorplanning）是當中的第一個步驟。根據不同的設計限制，平面規劃安排每個區塊的位置並且對於評估一些關鍵性的設計度量非常地有幫助，像是預測晶片面積、功率消耗、關鍵路徑的邊界以及總導線長度等等。 導線的連線長度對於時脈最佳化是一個很重要的指標。為了確保晶片效能，我們必須限制住關鍵導線的長度以滿足時脈要求。針對非關鍵連線的最佳化處理，非曼哈頓結構（non-Manhattan structure），像是X或Y結構，已被提出討論且可大量的降低實體資源的使用。然而，擺置與繞線步驟是在平面規劃之後執行，設計的佈局又由平面規劃所決定，因此，我們需要提早考量導線最佳化的問題，尤其是在實體設計初期的平面規劃階段。此外，在系統單晶片（system-on-a-chip，SoC）設計中，使用電壓島（voltage island）技術以降低功率消耗最近開始受到歡迎。目前這項技術僅被考慮在系統層級架構或在擺置流程完成之後的階段。在階層式設計與可重複使用之半導體智慧產權（intellectual propoerty，IP）廣泛的使用之下，為了得到較佳的初步結果，必須提早在平面規劃/擺置階段考慮電壓島的產生以降低功率消耗問題。 在本論文的第一部份，在平面規劃階段我們提出兩個考量不同設計限制的演算法。第一個演算法在平面規劃時，針對X結構繞線，加入了等腰直角三角形以及等腰梯形的新區塊形狀。本方法可更進一步的處理任意區塊，只要該區塊可被分割成矩形以及等腰直角三角形。第二個演算法在平面規劃階段考量電壓島的產生以及滿足效能限制，此限制是限制住關鍵連線的範圍。實驗結果說明本方法非常的有效率，在滿足時脈要求下，可同時的考慮功率繞線代價以及功率消耗的取捨。 在另一方面，晶片設計的第一次矽晶片的成功率越來越低，而利用失敗晶片以改善下次矽晶片的良率是很重要的一件事情。測試性設計（design-for-test，DFT）以及除錯化設計（design-for-debug，DFD）這兩種電路通常都在邏輯合成階段被加入設計電路之中。利用這些電路，我們可在製作矽晶片之後對設計的功能性進行驗證及確認正確性。由於資源的限制，DFT以及DFD電路僅能提供內部電路訊號的一小部分，我們需要其他方式來得到更多的訊息以便進行錯誤分析。聚焦離子束（Focus-Ion-Beam,FIB）是可在矽晶片製造完成之後，獲取內部導線信號技術中的一種技術。而隨著技術的逐漸進步、製程的縮小，FIB技術的解析度卻沒有隨著製程的快速縮小。因此，對於先進技術而言，經由FIB所能觀察到的導線以及能被修改的電路，在比例上明顯地降低許多，並且限制了很多在除錯過程中可藉由FIB技術所檢查的訊號。 本論文的第二部份介紹一除錯化設計的架構，藉由在後繞現階段（post-routing step）調整實體佈局以增加可被FIB觀察及可被FIB修改之訊號比例。根據設計規則及時脈要求，本實體佈局調整方法使用預先定義好的一些簡單操作方法，因此，本設計架構不需要複雜的繞線器（router）做為核心並且可被整合入目前任一的APR軟體。根據使用90奈米函示庫所獲得的實驗數據，本除錯化設計架構有效地增進可被FIB 觀察到或是修改的訊號比例，即便在不同的FIB參數設定下，仍可維持相同的使用面積以及晶片效能。

In the IC-design flow nowadays, the physical design is the critical stage which implements the design from gate-level netlist into geometric layout. Floorplanning is the first step in physical design. According to different constraints, floorplanning step arranges the location of each block and is useful to estimate some critical design metrics, such as area, power consumption, boundaries of critical paths, and total wirelength.

The wirelength of nets is an important issue for timing optimization. To maintain the chip performance, we have to bound the wirelength of critical nets for meeting timing issues. To minimize the total wirelength, non-Manhattan structures, such as the X and Y architectures, propose different flavors in reducing the use of physical resources. However, the placement and routing steps are after floorplanning step and the layout of design is decided by floorplanning step. Thus, we need to consider wirelength optimization at floorplanning step for reducing wirelength. Besides, using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become popular recently. Currently this approach has been considered either in system-level architecture or post-placement step. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/placement methodology considering voltage islands generation to solve power consumption problems.

In the first part of this dissertation, we present two algorithms considering design constraints at floorplanning step. The first algorithm deals with isosceles right triangular and trapezoidal blocks for X-architecture routing strategy. This approach can be further applied to pack with any block, which can be divided into rectangles and isosceles right triangles. The second one handles floorplanning considering voltage islands generation and performance constraints, which restrict the boundaries of critical nets. This method is flexible and can be extended to hierarchical design. The experimental results show that our method is not only effective in meeting performance constraints but also simultaneously takes the consideration about the balance between power routing cost and total power dissipation.

On the other hand, the first silicon of design is often failed and using failed chips to improve the yield for next silicon is very important. The design-for-test (DFT) and design-for-debug (DFD) circuits are often generated and integrated during logic synthesis stage. With these circuits, we can verify the functionality of design after manufacturing. Because of limitation of resource, the DFT and DFD circuits only deliver a small portion of internal signals and we need other approaches to get more information for failure analysis. The focused ion beam (FIB) is one of techniques to obtain the signals after manufacturing chips. While the technology node continually and aggressively scales, the resolution of FIB techniques does not scale as fast. Thus, the percentage of signals which can be observed through FIB probing is significantly decreased for advanced process technologies, which limits the candidates that can be physically examined through the FIB techniques during the debugging process.

The last part of the dissertation introduces a methodology to modify the layout and increase the signals for FIB observation. In the post-routing step, the layout modification is made through pre-defined simple operations subject to design rules and timing constraints. Hence, the proposed methodology does not require a complicated router as its core and can be applied to the layout generated with any commercial APR tool. The experimental result based on an 90nm technology has demonstrated that the proposed methodology can effectively increase the number of signals for FIB observation while the overall area and circuit performance remain the same.