薄膜電晶體之光電特性研究

Abstract

首先本論文使用了一種具有金屬遮光層(Metal shielding layer)的低溫多晶矽薄膜電晶體元件結構，並利用此結構來研究光漏電流的基本機制。利用遮蔽區域的不同，來控制改變低溫多晶矽照射的區域。由實驗結果可知，光漏電流主要源自於汲極端附近的多晶矽。當低溫多晶矽元件在只有汲極端受光照射下，此元件具有最高的光漏電流，但元件的次臨界擺幅並受到沒有很大的影響。然而當只有元件的源極端照射到光的情況下，汲極端所施加的電壓能顯著的影響元件的光漏電流與次臨界擺幅。在只有源極照射的元件結構下，由於電極偶合效應的關係，遮蔽金屬層能偶合汲極端的電壓至金屬遮蔽層中。藉由電壓偶合的效應，源極端受光所產生的電子電洞對能被有效的分離，因此能留下電洞於源極端。而越多的電洞若能累積於源極端，元件的次臨界擺幅就會劣化的越嚴重。除此之外，在此論文中也參考了文獻中所提到的分析模型，利用此模型來進一步的對光漏電流進行分析並萃取相對應的參數。最後依據所萃取的參數與實驗中的數據，提出了一個能帶圖用以解釋次臨界擺幅在受光下劣化的原因。 接著，從第一章的結果可知中光漏電與通道底部有極大的關係，因此我們將對元件通到底部做一些額外的處理，藉由引入些許缺陷來產生電子電洞對的複合中心。除了氨電漿可被利用來對緩衝層的頂部處理之外，同時氬氣的離子佈值也用於處理緩衝層的表面，並利用氬氣處理的實驗結果來證明，氨電漿處理手法可以達到相同的結果。若元件經過氬氣處理後，元件的光漏電流再受光強度5620nit的照射下能降低到8.6pA，且次臨界擺幅的劣化能抑制到46.4%。反之，若元件在沒有經過任何處理下，元件的光漏電流即使只在光強度2160nit照射下，光漏電流卻高達13.6pA。然而，在現今的多晶矽的元件製程中，通道摻雜的手法常使用於調變元件的臨界電壓。為了能更進一步的簡化元件製成，並不改變整體元件製作的流程下，我們也嘗試改變通道摻雜時離子佈植的條件，來使元件同樣能得到低光漏電流的特性。 此外，除了研究多晶矽元件的光漏電流特性之外，元件在受光下對可靠度的影響也被詳細的探討。在直流電壓下可靠度測試的實驗結果中可知，光所產生的額外電子電洞對能有效的降低汲極端的電場。而當有效電場能被進一步的降低時，將會使得多晶矽元件在受光下的直流電壓測試可靠度能進一步的提升。而照光所產生的電子電洞對能有效降低電場的假設，能藉由量測四端點元件在受光下的底極端的電流值來加以佐證。然而，在交流電壓可靠度的測試中，卻發現受光所導致的電場降低現象，並不能改善元件在交流電壓下的可靠度。這是由於縱使元件在受光時能產生額外的電子電洞對，但相對的這些額外的載子當交流偏壓切換到電壓低點時下，若載子仍存在於元件通道中的話，將造成額外的載子能藉由電場得到能量並撞極元件造成缺陷。 為了改善傳統非揮發性記憶體SONOS元件的抹除效應，本論文中提出了一種新式的元件結構，此新式結構是將基底接觸引入做為改善非揮發性記憶體SONOS的抹除效率。基底接觸抹除方式為利用記憶體的源/汲極(source/drain)與重摻雜基底間的順向偏壓，將重摻雜基底中的多數載子注入到基底(body)上，再利用閘極與基底的逆向偏壓所產生的電場來增加載子的速度，因此使得基底的載子能獲得足夠的能量，克服氧化層能障，最後載子到達電荷儲存層完成抹除。利用此基底接觸注入方式，可大幅減少抹除記憶體所需電壓以及時間。另外基底接觸的抹除方式和穿隧氧化層的厚度關係較小，可採用較厚的穿隧氧化層兼顧記憶體的抹除特性並維持記憶的保存能力(retention)，形成新穎的非揮發性記憶體元件的抹除方式。除此之外，此新式結構的製作流程能相容於現有的多晶矽元件製造流程，並不會增加任何無外的步驟。 除此之外，在本論文中也採用了溶膠凝膠的塗佈方式來製作氧化物半導體元件。然而無論是使用哪一種方法製作的氧化物半導體元件，此元件都會存在不穩定的電性表現，而造成這不穩定現象的主要原因是氧化鋅表面對氣氛的化學反應。無論是元件的基本特性、可靠度、磁滯現象或是變溫量測的結果都會受到氣氛影響。在此論文的最後，將對此基本理論做一個仔細的探討，並基於實驗的結果下，提出一種新式的處理手法。此新式的處理手法能改善元件隊氣氛的敏感度，並大大的改善元件在可靠度上的表現。

In order to investigate the mechanism of photo leakage current of poly-Si TFT, the poly-Si TFTs with patterned metal shielding layer are used to study. The location of the exposed region in poly-Si layer is defined by employing the proposed structure. The exposed region’s photo leakage current increased at the drain junction location; therefore, the drain junction was the effective area in inducing photo leakage current under light exposure. The drain-exposed poly-Si TFT exhibits a significantly high photo leakage current and a slight subthreshold swing degradation under illumination. However, the exposed region located at the source junction significantly degraded at the sub-threshold swing of TFT under illumination with an increase in drain bias. In other words, the accumulated holes will, however, affect the applied gate voltage at the source junction and cause the degradation of the S.S. in the poly-Si TFTs under illumination. Besides, the analytical model was applied to extract the parameters. Based on the experimental results and analytical parameters, a band diagram was proposed to explain the degradation of subthreshold swing. Next, the interface treatment is applied at the bottom interface surface between poly-Si film and top buffer layer in the poly-Si TFTs. The NH3 is used to serve as the treatment gas. In order to verify the proposed method, the Ar ion implant is also used to treat the interface. From experimental results of the Ar ion implantation device, the maximum degradation of sub-threshold is 46.4% and the photo leakage current is about 8.6pA under the 5620nit back-light illumination. However, the photo leakage current of conventional device exposed to the 2160 back-light brightness was about 13.6pA. By introducing the trap states, the excess electron-hole pairs would have probability to recombine at the defect sites to decrease the photo leakage current and moderate the degradation of sub-threshold swing. Besides the Ar ion implantation is used to treat the interface, the NH3 gas plasma also can be applied at the interface to create defect states. However, the channel doping is usually applied for modulate the threshold of poly-Si TFTs. In this study, the photo leakage current of poly-Si TFT with channel doping modulation is also investigated. By adjusting the implantation energy, the target depth of the implantation set at the interface. The device with the channel doping modulation has the best result of the photo leakage current. Third, the stability of poly-Si TFTs under both darkened and backlight illumination environments is investigated. The stability tests include DC hot-carrier stress and dynamic AC stress. In the DC hot-carrier stress, the experimental results showed the ON-current degradation under the backlight illumination was slightly higher than the darkened environment. The extra electron-hole pairs, generated by the back-light illumination, would influence the electric field near the drain junction and they would also reduce the channel-hot-carrier stress. Besides, the four terminal devices n-channel poly-Si TFT with counter-doped lateral body terminal was applied in order to monitor the hole current generated by the ionization impact near the drain junction. In the other part, both conventional and patterned metal-shielding structures are used to verify the reliability of the poly-Si TFTs under darkened and illuminated dynamic AC stress. Experimental results indicate that during the illuminated stress the competitive mechanisms of carrier increase and electric field reduction are generated. Forth, the lateral body terminal Silicon-Oxide-Nitride-Oxide-Silicon Thin-Film-Transistors (LBT SONOS TFTs) is proposed to enhance the erasing efficiency. This device has superior erasing efficiency by gate as well as lateral body electrode exerting bias. The erasing mechanism of LBT SONOS TFTs has been illustrated by the energy band diagrams. Holes gain sufficient energy by electric field in deep depletion region to surmount the tunneling oxide barrier because of exerting body bias under erasing operation. Also, the lateral body terminal exerting bias can enhance erasing efficiency and which is confirmed by different erasing conditions and structure. In addition, to verify the hole current injecting from the lateral body site, the size effect of LBT SONOS TFTs is also discussed. In addition, the hump phenomenon presents at large width of the LBT SONOS TFTs after erasing operation has also been discussed and explained it with the schematic diagram. Besides, the fabrication of SONOS-TFTs with lateral body terminal is quite easy and involves no additional processes. Such a SONOS-TFT is thereby highly promising for the future system-on-panel display applications. Fifth, the sol-gel spin-coating method is used to fabricate the Zr or Sn doped zinc oxide based thin film transistor. Regardless of the deposition method, all undoped ZnO conducting films have unstable electric properties in the long term. This stability is related to the change in surface conductance of ZnO films under oxygen chemisorptions and desorption. The gas ambient effect on the photo leakage current、the electrical characteristic of bias temperature、gate bias stability and hysteresis of transfer characteristics would be investigated. Last, a brief review of the mechanism of chemisorbed and physically adsorption would be discussed. Based on the mechanism and the above experimental results, a new method would be proposed to remove the chemisorbed and physically adsorbed of oxygen. In the proposed method, the light, heat, and vacuum environment were employed simultaneously. This proposed method is based on that the photo generated holes could easily migrate to the chemisorptions site due to the built-in electric filed and transition from chemisorbed state to a physisorbed state. The heat is used to overcome the van der waal force. Besides, the environment should in a vacuum environment to ensure that the desorbed oxygen could be evacuate from the chamber. By applying the proposed on the ZnO-based devices, the stability of the ZnO-based devices were greatly improved. Furthermore, these results can be as important information for the subsequent passivation process concerning the pre-treatment of the active layer.