高速可變長度快速傅立葉轉換處理器設計

Abstract

近年來，寬頻無線通訊應用正迅速地朝向提供更高的資料傳輸量來發展，所以越來越多的無線通訊系統需要更高的取樣率來滿足傳輸大量資料的需求。而在無線通訊系統中,快速傅立葉轉換(FFT)處理器被廣泛的使用。硬體成本、功率消耗以及資料產量是設計FFT處理器的重要議題。在這篇論文中，我們提出一個新的可變長度FFT處理器。我們設計的FFT處理器是採用多重平行資料路徑方式來提高資料產量，但由於多重平行資料路徑方式會明顯的提高硬體成本。因此，我們基於資料回授與硬體重複使用的觀念設計了Multi-path Delay Feedback (MDF)的FFT架構來同時兼具Multi-path Delay Computator (MDC) FFT架構的高資料產量與Single-path Delay Feedback (SDF)架構的低硬體成本的優點。我們結合多重平行資料路徑方法與MDF架構完成了我們的可變長度FFT處理器。我們將設計的可變長度FFT處理器透過台積電的65奈米製程來實現，所得到的晶片核心面積為0.821×0.817 mm2，我們的FFT處理器只需在165MHz的頻率下運作，效能表現即可滿足IEEE 802.11ad所要求的2.64G sample/s，因此我們的FFT處理器是符合下一代高效能無線通訊系統的要求。

In recent years, the broadband wireless application is developed rapidly for providing higher throughput, more and more wireless communication systems require higher sampling rates for transferring a great deal of data. The Fast Fourier Transform (FFT) processors are widely used in wireless communication system. And the hardware cost, power consumption and throughput are important issues for the design of FFT processor. In this paper, a novel pipelined variable-length multiple-path delay feedback (MDF) FFT processor has been proposed. MDF FFT architecture associates the advantages of single-path delay feedback (SDF) architecture and multi-path delay computator (MDC) architecture. Based on the concept of data feedback and hardware reuse, the hardware costs of memory and complex multiplier can be saved in our design. And the performance results of proposed variable-length FFT processor show that the data throughput rate is as high as 2.64G samples/s. The proposed variable-length FFT processor designed in a TSMC 65nm 1P6M CMOS process can meet IEEE 802.11ad standard at the operation clock rate of 165MHz. The proposed FFT processor is expected to be incorporated in next-generation high-performance wireless communication systems.