| 標題: | A NEW FAST ONE-PASS THINNING ALGORITHM AND ITS PARALLEL HARDWARE IMPLEMENTATION |
| 作者: | CHEN, CS TSAI, WH 資訊科學與工程研究所 Institute of Computer Science and Engineering |
| 公開日期: | 1-Jul-1990 |
| URI: | http://hdl.handle.net/11536/4078 |
| ISSN: | 0167-8655 |
| 期刊: | PATTERN RECOGNITION LETTERS |
| Volume: | 11 |
| Issue: | 7 |
| 起始頁: | 471 |
| 結束頁: | 477 |
| Appears in Collections: | Articles |
- Employing pipelined thinning architecture for real-tire fingerprint verifier / Hsiao, P. Y.;Chen, X. Z.;Lin, C. C.;Hua, C. H.;Chang, C. C.
- Parallel distance transforms on a linear array architecture / Chia, TL;Wang, KB;Chen, Z;Lou, DC
- Parallel execution of a connected component labeling operation on a linear array architecture / Wang, KB;Chia, TL;Chen, Z;Lou, DC
- 多重配送處理器架構下的延伸指令集探索 / 陳志遠;單智君
- An efficient binary motion estimation algorithm and its architecture for MPEG-4 shape encoding / Al-Qaralleh, Esam A.;Chang, Tian-Sheuan;Lee, Kun-Bin
- Architecture Design of Belief Propagation for Real-Time Disparity Estimation / Tseng, Yu-Cheng;Chang, Tian-Sheuan
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