具獨立雙閘極之多晶矽奈米線薄膜電晶體的研製與分析

Abstract

本篇論文提出一簡易且低成本之製作多晶矽奈米線元件的方法。此法的特點在於利用將電感耦合電漿式(inductively coupled plasma)蝕刻機台中的偏壓電源(bias power)關閉並搭配使用六氟化硫(SF6)的氣體以得到一具等向性與高蝕刻選擇比的蝕刻條件。將此參數用以側向蝕刻臨場摻雜多晶矽後便可形成寬度在10奈米~100奈米之向內凹陷的空隙，進而定義出奈米線的線寬。另外，當奈米線形成後，如果再沉積上第二層的介電層與閘極材料，此元件就具有獨立雙閘極的結構，可使元件的操作彈性大幅提升。 首先藉由控制側向蝕刻的時間，我們製備了具有不同寬度的奈米線元件，用以探討奈米線尺寸對元件電性的影響。與兩種單閘操作模式相比，實驗發現當奈米線越窄，在雙閘操作模式下電性改善的程度會有顯著的增加。經由量測分析，可得知這是由於奈米線尺寸會影響多晶矽的晶界能障受閘極調控的程度所導致。然而為了避免通道受到摻雜，原本所設計之元件製程卻會造成源/汲極的串聯電阻過大。因此，我們提出一種改良的流程，將臨場摻雜多晶矽取代離子佈值做為形成源/汲極區的製備方法。採用此技巧所完成的元件除了具有明顯改善的導通電流與漏電流之外，更能夠達到只有73 mV/dec的次臨界擺幅(subthreshold swing)，這是目前文獻上多晶矽元件最佳的成果。 除了最佳化製程以改善元件特性外，為了探討奈米線載子傳輸特性，本研究也在製程中引入電子束微影技術，進而將通道長度微縮至100奈米以下，同時搭配低溫量測設備來完整分析元件導通機制。研究發現，當測量溫度低於約100 K時，有一單閘模式下的轉換曲線會展現出低於傳統金氧半場效電晶體(MOSFET)極限的次臨界擺幅，而且此現象只發生在通道長度小於100奈米的元件。經由模擬及實驗證實，這個效應是來自於閘極經過離子佈值後，雜質分佈不均而導致閘極對通道的控制能力會隨通道位置改變而變化，因此沿通道方向的能帶圖會形成一類似駝峰的曲線所致。 有鑑於近來三維記憶體技術多使用多晶矽做為主動層，本研究也討論獨立雙閘多晶矽奈米線結構應用於矽-氧化矽-氮化矽-氧化矽-矽(SONOS)非揮發記憶體時所衍伸的價值與各種操作上的可行性。首先，量測上發現當進行寫入/抹除時，除了在主動閘施加一偏壓外，寫入/抹除的速度會隨輔助閘偏壓的增加而明顯加快，其原因來自於輔助閘偏壓能夠有效的影響奈米線中的電子密度，因而影響穿隧電子的數目與其效率。另一方面，本研究所製作的記憶體元件其雙閘極介電層材料分別為二氧化矽與二氧化矽-氮化矽-二氧化矽，當採用具二氧化矽介電層之閘極為讀取閘時，寫入/抹除態的感測窗口會展現出與輔助閘施加偏壓的相關性，然而此現象並不會在傳統上以二氧化矽-氮化矽-二氧化矽為介電層之閘極做為讀取閘時發生。研究發現其根本原因為背閘效應(back-gate effect)。於此架構下，我們做了許多此兩種讀取模式的操作特性比較，包括寫入/抹除速度、保持性與耐操性。最後我們嘗試將二氧化矽-氮化矽-二氧化矽同時做為雙閘極之介電層材料以驗證單一元件具有二位元儲存(2-bit/cell)的可行性。

A simple and low-cost method of fabricating poly-Si nanowire (NW) devices is proposed in this dissertation. The feature lies in turning off the bias power in an inductively coupled plasma etcher combined with the addition of SF6 gas to obtain an isotropic etching recipe with high selectivity. A re-entrant 10~100 nm wide cavity inside the in situ doped poly-Si could then be formed with this recipe, which in turn determines the feature size of the NW. Following the formation of NWs, another gate stack could be deposited and patterned such that the device has two independent gates that help increase the functionality and flexibility of device operation. To investigate the influence of the size of NW on device characteristics, NWs with varying widths were fabricated by controlling the duration of lateral etching. It is observed that as the NW gets narrower, the performance of double-gated mode would be enhanced to a larger extent compared with that of two single-gated modes. The root cause is identified to be related to the fact that the modulation rate of grain boundary barrier height of poly-Si by the gate is dependent on the NW dimension. Nevertheless, in order to avert inadvertent channel doping, the original device process flow is designed in a way that the series resistance of the source/drain may become too significant. In this regard, we propose a modified version of process in which in situ doped poly-Si replaces ion implantation for forming the source/drain regions. Devices fabricated with this approach demonstrate evidently improved on- and off-current. What’s more, a record-breaking value of subthreshold swing as low as 73 mV/dec could be obtained. In addition to process optimization to better the device performance, in an attempt to probe into carrier transport characteristics of NW, e-beam direct writing is adopted in our process as well to reduce the channel length below 100 nm. Meanwhile, cryogenic measurement facilities are employed to provide a comprehensive analysis on device transport behavior. It is found that as the temperature of measurement is lower than 100 K, one of the single-gated modes displays subthreshold swing that is well below the theoretical limit of MOSFET. Plus, this kind of phenomenon is only exclusive to devices with channel lengths shorter than 100 nm. With the aid of simulation and experimental verification, it is identified that this intriguing effect is caused by the non-uniform distribution of dopants introduced by ion implantation such that the controllability of gate over the channel is a function of location along the channel and the electrostatic potential of the channel would exhibit a hump-like profile. Given that most of the state-of-the-art 3D memory technology employs poly-Si as its active layer, the merit and operational feasibility coming from the implementation of independent double-gate scheme on SONOS non-volatile memory devices are also investigated. During programming/erasing, apart from the biases applied to the active gate, experimental results indicate that the programming/erasing speed is a monotonically increasing function of the auxiliary gate bias. This may be due to the electron density within the NW channel that the auxiliary gate helps modulate, which in turn affects the number of tunneling electrons and the programming/erasing efficiency. The device fabricated has oxide and oxide-nitride-oxide stack as dielectrics for two independent gates, respectively. The VTH window between P/E states shows a strong dependence on the auxiliary gate bias when the gate with oxide as dielectric is used as the read gate, which is in contrast to the fairly constant VTH window observed in a conventional mode (i.e., the read gate is with oxide-nitride-oxide as dielectric). Back-gate effect is recognized to be the major mechanism in play. To further delve into the implications, several comparisons between those two feasible read modes are made, including programming/erasing speed, retention, and endurance characteristics. Finally, proof-of-concept 2-bit/cell feature is demonstrated by utilizing oxide-nitride-oxide stack as the dielectrics for both gates.