可測試性設計與內建自我測試技術於有線等效保密智財之應用與研究

Abstract

隨著半導體工藝的進步，一顆單晶片上擁有數百萬邏輯閘的時代已經來臨。也因此，從事可重複使用的智財﹙IP﹚設計在當前的SoC設計上已經是一種趨勢。然而，在面對如此龐大的電路，尤其是內部的獨立模組，該如何有效且完整的測試著實是一個很大的問題。在本論文中，吾人透過實作來證明“內建自我測試技術”﹙BIST﹚在當前的智財設計中有相當的重要性，並倡議設計者在從事智財設計時應該要將“內建自我測試技術”列入設計的考量。 本論文從事的實作有︰首先設計出一個符合 IEEE 802.11 標準的“有線等效保密”﹙WEP﹚智財；再針對此智財運用各種設計上的技巧，設計出一個可以滿足工業規格的內建自我測試模組，來進行相關的測試與分析。最後，再拿這個內建自我測試模組與一般業界常用的傳統測試方法做分析比較，以期將本論文的實作結果提供給將來從事“內建自我測試技術”研究的讀者做為參考。

Due to the advance of the IC technology, we have entered the era of chips of multimillion-gate. It is a trend to design modern System-on-a-Chip (SoC) by using reusable intellectual properties (IPs). However, testing is a very difficult problem on a multimillion-gate chip, when it is composed of embedded cores such as IPs especially. In this thesis, we propose and demonstrate a built-in self-test (BIST) module for an IP, trying to ease this testing issue. First, we design a reusable “wired equivalent privacy” (WEP) IP based on the IEEE 802.11 standard. Then, in order to test and qualify this IP, we employ the BIST strategy, accommodating some design skills, used in the IP design, to test the IP. Analysis on this strategy has been done to compare it with the traditional testing technique such as scan in terms of fault coverage and hardware overhead. The experience and information obtained will serve as valuable reference to those who engage in BIST research and practice.