對於K頻段互補式金氧半射頻前端電路內超低功率集成元件之研究與設計方法

Abstract

由於對無線通訊產品的需求快速成長，以及射頻電晶體操作速度的顯著提升，近年來通訊標準的發展逐漸朝更高的頻率推進。另一方面，無線通訊產品對於高度可攜性與長待機時間的需求，也使得低功率的類比與射頻電路設計吸引越來越多的重視。可以預見的是，能夠整合多個通訊頻段並且對硬體設施與功率需求較低的系統，將在未來的射頻電路設計扮演重要角色。 本論文提出多種可應用在射頻前端電路中的低功率電路設計，這些技術主要為18~26 GHz之間的K頻段接收機所研發。首先是一種具備雙重振盪模式的電壓控制振盪器。此電路的一個主要的優勢在於所產生的雙頻振盪訊號可具有較寬的頻率差距，因此可利用於整合不同通訊標準下的射頻系統至單一硬體設備。除此之外，本論文闡述兩種可用於K頻段電壓控制振盪器與降頻混頻器的低功率技術。這些技術有助於減少現有多頻段系統的所需電路區塊、系統總功率消耗與晶片面積。本論文包含三個主要部分：第一個部分介紹在0.18μm 1P6M CMOS製程中設計之10/22GHz雙頻帶振盪器。此振盪器的頻段選擇係由一個特殊的開關電感所控制；其中電感的自我諧振機制被利用於改變電感的品質因素及實現頻率切換。在使用開關電晶體的一般切換式LC-VCO中，不同頻帶間的頻率切換範圍是相對較小的，而且很難同時對所有的頻段進行共振腔品質因素的最佳化。這些缺點可以在所提出的頻帶切換技術中得到大幅度的改善。 當操作頻率上升時，被動元件的品質因素下降對於電壓控制振盪器的現有低功率架構，例如變壓器回授組態而言，是一個主要的設計挑戰。除此之外，寄生電容也將顯著的限制高頻LC-VCO的調頻範圍。為了克服這些問題，本論文的第二部分提出一種具高效率與低功率90-nm CMOS電壓控制振盪器，此設計又稱為「可變偏壓技術」。此振盪器包含多重並聯之交互耦合對，但各子振盪器的操作與否則視不同頻率範圍內共振腔品質因素而定。在一給定的相位雜訊規範下，此振盪器可提供維持振盪所必需的負組，而能使不同頻率範圍內的功率消耗需求最小化。此電路的設計目標是對相位雜訊(在中心頻率1-MHz頻偏處達到約-110dBc/Hz)、調頻範圍(>10%)以低功率消耗(<5mW)進行最佳化。量測結果顯示所設計的電壓控制振盪器的功率消耗在全頻段內低於3mW，同時調頻範圍約在12%，是目前極少數設計能以變壓器回授組態而達到10%以上調頻範圍的低功率K頻段振盪器。 目前，最常被使用的主動混頻器架構係建構於雙平衡式吉伯特單元，這是因為此電路具備多項優點，諸如提供轉換增益，良好的埠間隔離度與極佳的偶次諧波壓抑能力。然而，其堆疊式的結構不利於操作電壓微縮之趨勢，則是一個建構低功率系統時的顯著缺點。雖然各種改進架構，例如電流輸送混頻器與折疊式混頻器都能夠舒緩此問題，但其因為暫態電流而產生之功率消耗仍將存在。另外，電流輸送混頻器與折疊式混頻器同時也遭遇寄生電容增加與較高之間接閃爍雜訊等問題。在本論文中，一種使用橫向LO整流設計的改良型雙平衡式混頻器被提出；此混頻器被製作於0.18μm CMOS製程中。當輸入訊號為21GHz而輸出訊號為20MHz時，測得之轉換增益接近5dB而輸入訊號之三階交調截距點約在2dBm。在1.3V的供應電壓下，此混頻器的功率消耗只有1.43mW，這約為其他已提出之K頻段主動混頻器的五分之一到十分之一。

Due to the rapid growth of the demand for wireless communication products and the significant improvement in the operation speed of RF transistors, the development of communication standards are increasingly toward higher frequencies in recent years. On the other hand, the requirements of high portable ability and long standby time of wireless communication products also result in low-power analog and RF designs attracting more attention gradually. It can be predicted that the system which is able to integrate multiple communication spectra and only requires less hardware implementation and lower power dissipation will play an important role in the future. This dissertation proposes several low-power circuit designs for RF front-end circuits, these techniques are mainly developed for K-band (18~26 GHz) receivers. First of all, a voltage-controlled oscillator (VCO) that has dual-resonant mode. One major advantage of this design is that the circuit can generate two oscillation frequencies with wide frequency-spacing, which can be utilized to integrate RF systems of different communication standards into a single hardware implementation. Besides, this thesis introduces two low-power techniques used for K-band VCOs and down-conversion mixers. These approaches are helpful to reduce the required circuit blocks, the overall power consumption and the chip area of present multi-band systems. The dissertation include three major parts: The first part introduces the designed 10/22 GHz dual-band 0.18-μm CMOS oscillator. The band-selection of this VCO is controlled by a novel switchable inductor; the self-resonance mechanism is utilized to change the inductor quality-factor and achieves band-switching. In a conventional switched LC-VCO using a switching transistor, the frequency-switching-range is relatively small and it is difficult to optimize tank quality factor at all frequency bands. These drawbacks can be substantially improved in the proposed novel band-switching technique. When operation frequency increases, the quality factor degradation of passive components is a major issue for existing low-power VCO architectures, such as transformer-feedback topology. Furthermore, parasitic capacitance also significantly restricts the tuning range of high-frequency LC-VCOs. To address these issues, the second part of this thesis proposes a 90-nm CMOS VCO with high-efficiency and low-power properties, which is called “bias-varied technique”. The proposed VCO includes multiple parallel cross-coupled pairs, but the operation of numbers of sub-VCOs depends on the tank quality factor at different frequency ranges. Under a given phase noise criterion, this oscillator can provide the necessary negative-resistance to maintain oscillation; therefore the required power consumption can be minimized for different frequencies. The design target of this circuit is to optimize phase noise performance (~-110 dBc/Hz at 1-MHz-offset frequency), tuning range (>10%) and power consumption (<5 mW). The measurement results show that the power consumption of the designed VCO is lower than 3 mW at the whole tuning range, while the tuning range is about 12%. This is a rare design in present low-power K-band VCOs which uses the transformer-feedback topology and achieves a tuning range >10%. Nowadays, the most commonly used topology of active mixers is based on double-balanced Gilbert-cell, because of this circuit has several advantages as offering conversion gain, high port-to-port isolations and excellent even-harmonic rejection. However, the stacked configuration is unfavorable to the trend of voltage scaling, which is a significant drawback for constructing low-power systems. Although the modified topologies, such as current-bleeding and folded mixers, can relieve the issue of voltage compression but the power dissipation due to transient current eventually exists in these circuits. In addition, current-bleeding and folded mixers also suffer from increased parasitic capacitance and higher indirect-mode flicker-noise. In this dissertation, a modified double-balanced mixer using a lateral LO current commutation design is proposed; this mixer was implemented in a 0.18-μm CMOS process. When the input frequency is 21 GHz and the output frequency is 20 MHz , the measured conversion gain is near 5 dB and the input third-order-intercept point (IIP3) is about 2 dBm. The power consumption of this mixer is only 1.43 mW under a supply voltage of 1.3 V, which is from one-fifth to one-tenth of power dissipation of other reported K-band active mixers.