應用於Serial ATA之全數位展頻時脈產生器及數位可程式化之高斯時脈產生器

Abstract

在這篇論文中,我們聚焦於利用輸入調變方式的全數位時脈展頻電路.為了產生較快頻率以及較小頻率展頻量的調變時脈,我們提出了一個新的Domino調變方式.我們產生出來的調變時脈.可以提升至100MHz以及5000ppm的展頻量.相比之下,之前發表的論文其調變時脈只有 23MHz以及3%.在架構設計上,我們也提出一個新的粗細混何的數位延遲線.此架構相可以節省330%以及383%的功率消耗及面積.我們提出的數位展頻時脈產生器(AD-SSCG)有成為矽智財(IP)的潛力.因為其電路都是由數位電路所設計的.這個AD-SSCG矽智財被用來與一個 1.2GHz 以及一個 3GHz的PLL在做模擬,都可以成功產生展頻.最後我們把AD-SSCG與一個3GHz的PLL利用UMC 90奈米1P9M的製程實現.AD-SSCG所佔的面積是335um × 105um其功率消耗是2.9mW.利用hspice post-sim模擬3GHz的EMI下降量為22dB. 最後,我們提出的一個數位高斯時脈產生電路,它是設計給CDR作測試使用.高斯時脈生器使用了高斯雜訊產生器,並把這個雜訊轉換成一個高斯時脈.產生的高斯時脈有著調整它jitter大小的能力,以用來驗證CDR在不同環境的需要.我們將提出的高斯時脈產生器合成於FPGA發展板.我們可以將資料驗証量提升到1012筆,以驗證CDR的錯誤率.

In the thesis, we focus on the AD-SSCG (All Digital Spread Spectrum Clock Generator) modulation method with input reference. In order to achieve higher frequency and less frequency deviation, we propose a new Domino modulation method. We can improve the modulated clock to 100MHz and 5000ppm of frequency deviation as compared to 23MHz modulated clock and 3% of frequency deviation is published before. In the architecture design, we propose a novel Coarse-Fine DDLi (Digital Delay Line) structure, it improve the power and area by 330% and 383% than traditional structure. The AD-SSCG has the potential to become an IP because all of the circuits are deigned by digital circuit. This IP is used to work with a 1.2GHz and a 3GHz PLL, and both of them can spread spectrum successfully. Finally, our AD-SSCG and a 3GHz PLL are implemented with UMC-90-CMOS 1P9M process. The area and power of AD-SSCG are respectively 335um × 105um and 2.9mW, and the EMI reduction of 3GHz PLL is 22dB by hspice post-sim simulation. Finally, a proposed digital programmable Gaussian clock generator is designed for CDR (Clock and Data Recovery Circuit) testing. The Gaussian clock generator uses Gaussian noise generator to transforms a clock to a Gaussian clock. The generated Gaussian clock has the ability of controlled jitter to verify CDR with different environments. By using the proposed Gaussian clock generator on a FPGA board, we can easily verify the performance of the CDR to 1012 data to check the Bit ERROR Rate (BER).