無線都會網路之下行取樣頻率同步設計

Abstract

IEEE 802.16e為高速無線傳輸規格，其所採用的通訊技術為正交分頻多工（OFDM）與多輸入多輸出(MIMO)。正交分頻多工是一種多載波的調變方式，將資料分散到各個不同的頻率且互相正交的次載波。多輸入多輸出是使用多天線傳送與接收的技術。在本論文裡，我們專注於802.16e取樣頻率漂移，並使用與C語言建立系統模擬平台。此平台包含載波同步，時序同步與頻域等化器。在正交分頻多工和多輸入多輸出情況之下，我們提出了幾種模式來說明取樣頻率飄移的現象，並提出3個架構來補償取樣頻率飄移。最後，此論文提出有效率使用記憶體之取樣頻率飄移補償之架構。此架構可以減少記憶體使用量達85%，並能將頻率飄移在20 ppm以下的情況完全補償回來，而在40 ppm時所增加的誤差會小於0.01位元錯誤率。相對於未補償的情況在20 ppm與40 ppm時分別是0.15位元錯誤與0.36位元錯誤率，本論文提出之有效率使用記憶體之取樣頻率飄移補償架構大幅改進系統錯誤率。

IEEE 802.16e is a recently proposed standard for high speed wireless transmission. Orthogonal Frequency Division Multiplexing (OFDM) and Multiple-input Multiple-output (MIMO) technical is adopted in 802.16e. OFDM is a kind of multi-carrier modulation and data are divided into several differential and orthogonal subcarriers. MIMO is a kind of transmission way with multiple transmitting antennas and multiple receiving antennas. In this thesis, we focus on sampling clock offset (SCO) of 802.16e and build a simulation platform using C language. This platform contains carrier frequency synchronization, timing synchronization and frequency domain channel estimation, and we simulate SCO effect on this platform. We propose two kinds of model to illustrate SCO effects proposes three architectures to compensate SCO on OFDM and MIMO system. Finally, we propose a memory-efficiency architecture for sampling clock offset compensation. This architecture reduces the usage of memory by 85 %. This architecture can perfectly compensate SCO effect when SCO value is below 20 ppm, and make the BER less than 0.01 when SCO value is 40 ppm. However, without compensation, under 20 and 40 ppm SCO, the BER is 0.15 and 0.36 respectively. Thus, the proposed memory-efficiency architecture for sampling clock offset compensation improves the BER of the system significantly.