先進CMOS元件結構的解析模型建立－量子侷限效應及製程變異敏感度之探討

Abstract

本論文建立一個理論架構，以Poisson和Schr□dinger方程式的解析解為基礎，考慮量子侷限效應，探討多種先進元件結構的微縮性及對於製程變異的敏感度。這個理論架構包含多重閘極元件(Multi-Gate)、環閘極元件(Gate-All-Around)、超薄層通道元件(Ultra-Thin-Body)等先進元件結構，並可應用於使用高遷移率(high mobility)通道材料的元件。 利用三維Poisson方程式的解析解，我們可由靜電完整性的角度，比較多重閘極元件及環閘極元件的臨界電壓對於製程變異的敏感度。結論指出採用輕摻雜通道的環閘極元件受到製程變異及隨機摻雜擾動的影響最小。對於重摻雜通道的元件，摻雜數目的變異會決定元件的臨界電壓變異，而環閘極元件由於其較大的表面積-體積比(surface-to-volume ratio)，其臨界電壓受到摻雜數目變異的影響將會大於多重閘極元件。 當元件尺度更加微縮，我們利用Schr□dinger方程式的解析解，探討量子侷限效應對於短通道元件鰭狀電晶體及環閘極元件的臨界電壓變異的影響。結論指出，由於量子侷限效應，通道寬度變異對於極小尺寸的鰭狀電晶體及環閘極元件的重要性提升。對於採用不同通道表面方向鰭狀電晶體而言，(100)表面方向的矽元件及(111)表面方向的鍺元件在通道寬度變異時，表現出較低的臨界電壓敏感度。由於臨界電壓對通道寬度的敏感度會由短通道效應及量子侷限效應共同決定，因此環閘極元件的通道寬度可經由最佳化設計以減少臨界電壓變異。 利用Schr□dinger方程式的解析解，我們探討量子侷限效應對於超薄層通道元件及多重閘極元件的短通道效應的影響。結論指出，當元件的通道厚度小於某一臨界值時，量子侷限效應可改善超薄層鍺元件的臨界電壓下降(threshold voltage roll-off)。由於鍺通道較為顯著的量子侷限效應，超薄層鍺元件可能比矽元件有更小的臨界電壓下降。對於多重閘極結構，砷化銦鎵(InGaAs)通道的臨界電壓下降問題可被鰭狀通道高度(fin height)方向的量子侷限效應抑制，使其與鍺通道元件相比有更小的臨界電壓下降。此二維的量子侷限效應對於多重閘極元件的微縮性有顯著的影響。我們改變通道寬度及高度，觀察不同高寬比(aspect ratio)的元件，發現當元件的subthreshold swing相同時，三閘極(Tri-gate)電晶體由於其較顯著的二維量子侷限效應，比鰭狀電晶體(FinFET)有更佳的微縮性。 我們提供一個適用於高介電閘極絕緣層平坦式矽及鍺通道元件的量子侷限效應形成的載子層厚度(dark space)的封閉形式(closed-form)模型。這個模型對於(絕緣層及通道間)能障高度、表面電場、通道及閘極絕緣層中的等效質量等參數的相依性皆有良好的準確度。此模型亦適用於通道採用後退型摻雜(retrograde doping)的元件。此模型可應用於預測鍺元件考慮量子侷限效應後的subthreshold swing及臨界電壓上升量。由於量子侷限效應會放大摻雜擾動造成的臨界電壓變異，我們進一步建立了此量子侷限效應造成的倍增因數模型。利用此量子模型，我們可以更準確地評估各個參數(如有效氧化層厚度(EOT)、溫度等)對於摻雜擾動造成的臨界電壓變異的影響。 應用等效趨動電流法(effective drive current approach)，可分析隨機摻雜擾動(RDF)及線邊緣粗糙(LER)對於平坦式Bulk元件及鰭狀電晶體(FinFET)的切換時間(switching time)變異的影響。研究結論指出，對於平坦式Bulk元件，雖然隨機摻雜擾動被視為是臨界電壓變異的主要來源，但是當考量切換時間變異時，線邊緣粗糙的相對重要性會提升。對於鰭狀電晶體，雖然鰭狀通道寬度方向的邊緣粗糙被視為是臨界電壓變異的主要來源，但是當考量切換時間變異時，鰭狀通道長度方向的邊緣粗糙的相對重要性將會提升。

Based on the analytical solution of Poisson and Schr□dinger equation, this dissertation establishes a theoretical framework to investigate the device scalability and sensitivity to process variations considering the impact of quantum-confinement effects. This theoretical framework includes advanced CMOS device structures such as multi-gate, and Gate-All-Around (GAA), and Ultra-Thin-Body (UTB) devices, and can be applied to devices with high-mobility channel materials. From the prospective of electrostatic integrity, we compare the sensitivity of threshold voltage (Vth) to process variations for multi-gate devices with various aspect ratio (AR) and GAA device using analytical solutions of 3-D Poisson’s equation. Our study indicates that lightly doped GAA device shows the smallest Vth variation caused by process variation and dopant number fluctuation. For heavily doped devices, dopant number fluctuation may dominate the overall Vth variation. The Vth dispersion of GAA device may therefore be larger than that of multi-gate MOSFETs because of its larger surface-to-volume ratio. We also analyze the impact of AR on the Vth dispersion due to dopant number fluctuation for multi-gate MOSFETs. Using the derived analytical solutions of Schr□dinger equation for short-channel devices, we investigate the impact of quantum-confinement effect on the sensitivity of Vth to process variations. Our study indicates that, for ultra-scaled FinFET and GAA devices, the importance of channel thickness (tch) variation increases due to the quantum-confinement effect. For FinFET, the Si-(100) and Ge-(111) surfaces show lower Vth sensitivity to the tch variation as compared with other orientations. As the Vth sensitivity to tch for short-channel device is determined by the short-channel effect and the quantum-confinement effect, the tch of GAA MOSFETs can be optimized to reduce the Vth variation. The impact of quantum-confinement on the short-channel effect for UTB and multi-gate MOSFETs are investigated using the derived analytical solutions of Schr□dinger equation. When the tch is smaller than the critical thickness, the quantum-confinement effect may decrease the Vth roll-off of GeOI MOSFETs. Thus, Ge devices may exhibit better Vth roll-off than the Si counterpart because of the more significant quantum confinement. For multi-gate structure, by exploring the quantum-confinement effect along the Hfin direction, the Vth roll-off of InGaAs devices can be suppressed and become smaller than the Ge counterpart. This 2-D quantum-confinement effect is also crucial to the scalability of multi-gate device. Our study indicates that for a given subthreshold swing, Tri-gate (AR=1) with significant 2-D confinement effect exhibits better Vth roll-off than FinFET (AR>1). We provide a closed-form model of quantum “dark space” for Ge and Si MOSFETs with high-k gate dielectric. This model shows accurate dependences on barrier height, surface electric field, and quantization effective mass of channel and gate dielectric. Our model can also be used for devices with the steep retrograde doping profile. This physically accurate dark space model will be crucial to the prediction of the subthreshold swing and quantum-confinement induced Vth shift of advanced Ge devices. Using this closed-form dark space model, we also provide a closed-form model for the quantum-confinement induced amplification factor (AFQC) in Vth variation due to random dopant fluctuation (RDF). Using our model, various factors such as EOT and temperature that may modulate/reduce the impact of RDF on Ge and Si MOSFETs can be accurately assessed. The impact of RDF and LER on the switching time variations of bulk MOSFETs and FinFET have been assessed using the effective drive current approach that decouples the switching time variation into transition charge (□Q) and effective drive current (Ieff) variations. Our results indicate that for bulk MOSFETs, although the RDF has been recognized as the main variation source to Vth variation, the relative importance of LER increases as the switching time variation is considered. As for lightly-doped FinFET, although the impact of fin-LER is more crucial to Vth variation, the relative importance of gate-LER increases as the switching time variation is considered.