高性能多晶矽薄膜電晶體於三維積體電路與系統面板之研究

Abstract

在本篇論文中，探討應用於三維積體電路(3-D ICs)與系統面板(SOP)之高性能多晶矽薄膜電晶體。我們提出了幾種改善多晶矽薄膜電晶體應用於三維積體電路與系統面板特性的方法，並提出機制與元件模擬解釋。 首先研究利用金屬誘導結晶和準分子雷射結晶的底閘極多晶矽薄膜電晶體。發現在金屬誘導結晶的元件中，當主動層厚度增加或/和微縮元件尺寸時，元件特性會有改善，但是元件的均勻性卻劣化。我們提出一個基於水平和垂直成長的機制解釋金屬誘導結晶的底閘極多晶矽薄膜電晶體的厚度和尺寸效應。另一方面，由於在適當的雷射能量下，通道層中可以成長大型的橫向晶粒，所以準分子雷射結晶的底閘極多晶矽薄膜電晶體電特性的表現又比金屬誘導結晶的元件來得好。接著，提出利用準分子雷射結晶於具有一個新穎的氧化層梯機構，利用此結構也可以在通道中獲得大型的橫向晶粒，因此多晶矽薄膜電晶體的特性將大幅增加。單閘極的氧化層梯多晶矽薄膜電晶體電子和電洞遷移率可以分別達到300 cm2/V-s和150 cm2/V-s以上，這是傳統準分子雷射結晶元件的2.5倍以上。不僅如此，導入複閘極(dual-gate)的結構可以避開唯一的垂直晶界，並大幅增加氧化層梯的元件特性和均勻性。然而，在傳統準分子雷射結晶的複閘極元件中，由於晶界是隨機分佈，複閘極無法有效避開晶界，因此特性沒有有效提升。 再者利用此準分子雷射結晶底閘極多晶矽薄膜電晶體結構，應用於高性能雙位元矽-氧-氮-氧-矽(SONOS)型的非揮發性記憶體。藉由熱電子注入(CHEI)和帶對帶熱電洞注入(BBHHI)，由於具有較高的載子遷移率，準分子雷射結晶底閘極矽-氧-氮-氧-矽記憶體的寫入/抹除速度比固相結晶(SPC)元件快100倍。為了提升記憶體的儲存密度，我們提出具有雙閘極(double-gate)的準分子雷射結晶矽-氧-氮-氧-矽(SONOS)型的非揮發性記憶體可以達到每個單元擁有四個位元的儲存密度。由於它具有兩個通道，即上通道和下通道，因此每個通道可以儲存兩個位元。實驗發現，並可達到大的記憶體窗口(memory window)2.89V及小的水平與垂直干涉。 其次以準分子雷射結晶的多晶矽薄膜可以造成晶界突起，使晶界突出區附近電場增強，藉由凹陷通道型的矽-氧-氮-氧-矽(SONOS)型的準分子雷射結晶薄膜電晶體，我們可以在通道區獲得單一垂直晶界。當這個人為控制的垂直晶界位於通道的中間時，由於在晶界突出區附近電場增強的效應，準分子雷射結晶的元件就展現出比固相結晶的元件有較好的記憶體特性。進一步，我們也將這個垂直晶界控制位於源極或汲極，記憶體特性也大不相同。在寫入後，晶界位在源極的記憶體區間比晶界位在汲極的記憶體區間來得大。我們提出，在讀取時，由晶界和寫入電子合成的總能帶障，位於汲極會被拉得比位於源極低。透過元件模擬也證實了這個機制。 除此之外，我們亦探討準分子雷射結晶的多晶矽薄膜電晶體，應用於三維積體電路，提出兩種三維結構，都具有互補式的元件分別在上層與下層。第一種形式的準分子雷射結晶三維互補式反相器，以一個具有單一垂直晶界的底閘極多晶矽薄膜電晶體與一個具有上閘極多晶矽薄膜電晶體分別在下層與上層組成。它的電性優於固相結晶的元件。更進一步改良，提出第二種形式的準分子雷射結晶三維互補式反相器，兩層元件皆以具有單一垂直晶界的底閘極多晶矽薄膜電晶體構成，不論對於元件在上層或下層，都可以達到電子及電洞遷移率分別超過400 cm2/V-s及180 cm2/V-s。不僅如此，為了使互連導線更短，在微縮隔離氧化層的厚度時，發現下層元件的輸出電流有增加的趨勢，這有助於等尺寸的p型元件與n型元件的輸出電流匹配。這個增加的趨勢是由於雙閘極(double-gate)效應，我們也以元件模擬驗證這個效應。 綜之，我們成功的發展準分子雷射的結晶技術，製作高性能多晶矽薄膜電晶體，可應用於三維積體電路(3-D ICs)和系統面板(SOP)，其會影響多晶矽薄膜電晶體特性、非揮發性記憶體特性及三維積體電路的參數也均在本論文中詳細討論。

High-performance polycrystalline silicon thin film transistors (poly-Si TFTs) have been studied for the applications in three-dimensional integrated circuits (3-D ICs) and system on a panel (SOP). Several approaches were proposed to enhance the performance of the poly-Si TFTs, which was explained by the proposed mechanisms with device simulations. At first, the bottom-gate (BG) poly-Si TFTs were studied in virtue of metal-induced crystallization (MIC) and excimer-laser crystallization (ELC). In case of MIC, while increasing the active thickness increased and/or shrinking the dimensions, the electrical characteristics could be improved but the device-to-device uniformity was degraded. A possible mechanism based on the lateral and vertical grain growth was proposed to explain the effects of the device dimensions and active layer thickness of the BG poly-Si TFTs with MIC. On the other hand, the BG poly-Si TFTs with ELC exhibited better electrical characteristics than the devices with MIC due to the large lateral grains in the channel under appropriate laser irradiation energy density. Then, a novel oxide step structure with ELC was also proposed to produce large lateral grains in the channel region and, therefore, the single-gate oxide-step poly-Si TFTs could achieve high field effect mobilities above 300 cm2/V-s and 150 cm2/V-s for n-channel and p-channel TFTs, respectively, which were about 2.5 times higher than that of the conventional excimer-laser crystallized devices. Moreover, both the performance and uniformity were significantly improved for the oxide-step poly-Si TFTs in stead of the conventional ones as the dual-gate structure was introduced owing to avoiding of the single one perpendicular grain boundary. The BG poly-Si TFTs with gate-dielectric stack of oxide, nitride, and oxide crystallized via ELC were applied to demonstrate high-performance two-bit SONOS-type non-volatile memory. By means of channel-hot-electron injection(CHEI) and band-to-band hot hole injection (BBHHI), the program/erase speed of the BG SONOS TFTs with ELC were about 100 time faster than those of the devices with solid-phase crystallization (SPC) owing to their high field effect mobilities. To further multiply the storage density, the high-performance SONOS TFTs with double-gate structure (DG) have been also achieved to exhibit four bits per cell via simple ELC method. Since the DG SONOS TFTs with ELC have two channels, namely top and bottom channel, the 4-bit per cell was implemented by storing two bits in each channel. The experiment results demonstrated a memory window of 2.89 V with ignorable lateral and vertical interferences because of the CHEI program and partial depletion of channel for the DG SONOS TFTs. Moreover, the gain boundary protrusion can be formed the ELC, and, therefore, the electric field was enhanced near the protrusion. In the study of the grain boundary effects on the memory characteristics, the single one grain boundary protrusion in the channel was achieved by means of the recessed-channel (RC) SONOS TFTs with ELC. As the artificially controlled grain boundary located in the middle of channel, the memory characteristics of the RC-ELC SONOS TFTs were better than those of the SONOS TFTs with conventional ELC and SPC due to the enhancement of electric field near the grain boundary protrusion. On the contrary, when the artificially controlled grain boundary was located near one side junction, the memory characteristics differed from the grain boundary near drain junction and near source junction. After programming, a larger memory window was found in the device with one grain boundary near source junction as compared with the device with one grain boundary near drain junction. A series of device simulation was studied to support the mechanism that the total potential barrier height caused by the grain boundary and programmed charge was lowered more in the drain junction than in the source junction. In addition, the poly-Si TFTs with ELC were applied to three-dimensional integrated circuits (3-D ICs) applications. Two novel and simple 3-D structure with vertically-stacked complementary devices using ELC were proposed. The first type of 3-D CMOS inverter with ELC, which is composed of one BG poly-Si TFT with single one perpendicular grain boundary in the channel on the lower layer and one stacked top-gate (TG) poly-Si TFT on the upper layer, the electrical properties were better than those with SPC. To further improve, the second type of 3-D CMOS inverter with ELC, which is composed of BG poly-Si TFTs with single one perpendicular grain boundary on both layers, could achieve higher mobility about 400 cm2/V-s and 180 cm2/V-s for n-channel and p-channel devices, repectively. In addition, while compacting the separation oxide thickness, the output current of the devices on the lower was tend to be increased owing to the double-gate effect, which was verified with a device simulation. In summary, high-performance poly-Si TFTs have been developed to be potential to the applications in 3-D ICs and SOP. The parameters that affected the performance of poly-Si TFTs, non-volatile memory, and 3-D ICs were discussed in detail.