互補式金屬氧化物半導體延遲元件及其應用之研究

Abstract

隨著積體電路製程微縮至深次微米以及先進的電路技術持續發展，強化系統效能包含資料傳輸量及功率消耗必須藉由高度整合各種不同功能來持續驅動。為了達到完整系統整合以及成功地在內部或外部功能之間傳遞訊號，訊號時間的產生扮演著重要的角色。在現代互補式金屬氧化物半導體(CMOS)的電路設計中，延遲元件在產生訊號時間方面最為廣泛運用，其時間與功率表現對整個系統效能而言極為關鍵。 本論文首先提出一種在系統層級整合中能產生參考時間源的嵌入式矽振盪器。使用相對參考模型的方法可以在製程-電壓-溫度變異的影響下估計內部延遲元件的延遲時間。根據此方法，將可以在不需任何外部參考源的條件下補償製程-電壓-溫度變異對產生頻率的影響。在實作中，本論文設計數個不同應用需求取向的嵌入式矽振盪器。使用標準邏輯元件嵌入式矽振盪器具有低功率及小面積的優點，在固定供壓的條件下能產生頻率精準度0.2 %及標準供壓上下10 %的範圍條件內產生頻率精準度2.3 %。並且在供壓降低的情況下還能運作，現有的嵌入式矽振盪器的設計至少需要1.05 V的供壓，本設計可達到最低0.6 V的供壓。此外，本論文並設計基於源耦合式弛張振盪器的嵌入式矽振盪器來進一步強化在供壓變異的情況下的頻率精準度達0.83 %及降低功率消耗。 在頻率及相位的同步方面，使用所提出的遠端參考更正及接腳間延遲不匹配的修正可以達到單一晶片整合及資料量提高。遠端參考訊號可提供本地端頻率追蹤及相位對齊的時間資訊，在數個不同應用的實作中則採用了無線近身網路(WBAN)、通用序列匯流排(USB)、及雙倍資料率(DDR)等標準來驗證所提方案的可行性。在無線近身網路及通用序列匯流排的應用中，使用嵌入式矽振盪器達到頻率同步並且分別保持4.85 Mbps及 480 Mbps的高資料傳輸量。而所提出的交錯式遲滯元件可以減少功率及面積使用。在雙倍資料率的應用中，相位同步電路使得接腳間延遲修正的效能達到 200 Mbps/pin至1.6 Gbps/pin的速度範圍。 因此，本論文所提出的架構及電路不僅強化系統資料量並且降低功率消耗及面積使用，使得本方案非常適用於標準CMOS製程中的系統層級整合。

As IC process scales down to deep-submicron and advanced circuit technology continuously develops, the integration of various functions becomes more necessary to drive the system performance including system throughput and power consumption. For the complete system integration and the successful communication between interior or exterior functions, the signal timing generation plays an important role. In modern CMOS circuit design, CMOS delay cells are the most widely applied for the signal timing generation. The timing and power of the delay cell designs are critical to the overall system performance. This dissertation first proposes a standard CMOS embedded silicon oscillator, which can generate the timing reference, for complete system integration. By using the relative reference modeling method, the delay of the internal delay cells can be estimated under process-voltage-and-temperature (PVT) variations. Accordingly, the generated frequency can be compensated against the PVT variations without external references. In the implementation, several embedded silicon oscillators dedicated to various application requirements are designed. The all-digital embedded silicon oscillator with standard logic cells has low power and small area with the frequency accuracy of 0.2 % at fixed voltage and 2.3 % at the nominal supply ±10 %. In addition, it can still operate as the supply voltage scales down. The 0.6-V supply voltage is the least among the state-of-the-art embedded silicon oscillators, which are supplied by at least 1.05 V. The source-coupled relaxation oscillator based design further improves the frequency accuracy to 0.83 % against the voltage variation with less power consumption. In the frequency and phase synchronizations, architectures of the remote reference correction and the pin-to-pin delay mismatch deskew are proposed for both the single chip integration and the throughput enhancement. The remote reference signal provides the timing information for the local frequency tracking and phase alignment. The implementations for several applications including the wireless body area network (WBAN), the Universal Serial Bus (USB), and the Double Data Rate (DDR) are demonstrated to verify the feasibility of the proposal. In the WBAN and USB applications, the frequency synchronization is achieved to keep the high throughput of 4.85 Mbps and 480 Mbps, respectively, with the applied embedded silicon oscillators. The proposed interlaced hysteresis delay cells, which are suitable for the middle-to-low frequency applications, further reduce the power and the area. In the DDR applications, the phase synchronization circuits achieve pin-to-pin deskew performance in the range of 200 Mbps/pin to 1.6 Gbps/pin. As a result, the proposed architecture and circuits not only enhance the system throughput but also reduce the power consumption and area, making the proposal very suitable for system level integration in standard CMOS process technologies.