應用於無線近身網路之低耗能基頻處理器設計

Abstract

無線近身網路是利用感測器來蒐集各種身體訊號，並將訊號以無線傳輸的方式送至可攜式電子裝置以提供可靠的生理資訊。近年來已逐步應用於連續醫療照護，提升已開發國家醫療品質和健康監控範圍，並可進一步拓展至多媒體傳輸，滿足不同近身資料傳輸的應用。為了達到長期的身理訊號監測，可靠的訊號傳輸、低耗能和微型化為實現無線近身網路系統的基本需求。 考慮現存之近距離傳輸標準以及相關技術，在功率消耗上均難以滿足長時間的使用需求，且這些系統使用較低階的調變技術，無法提供穩定的生理訊號傳輸品質。因此，本論文藉由分析無線近身網路之運作行為，採用正交分頻多工的調變技術提升傳輸速率，讓系統在大部分時間以極低的速度處理和儲存生理訊號，待訊號累積至一定容量後以較高的傳輸速率於極短時間內傳送，減少收發器開啟的時間節省能源消耗；同時也提供使用者在不同情境和移動環境下之傳輸可靠度。在電路實作上，低操作電壓和系統傳輸速率(或收發器開啟時間)將同時被考量，以取得較高的能量利用率。根據各區塊的運作特性，採用多電壓區間搭配電源閘控制的方式，有效最佳化系統動態功耗和漏電流。本論文提出之基頻處理器已由90奈米標準CMOS製程實現晶片，此處理器可操作在0.5伏特，並提供最高9.7 Mbps的傳輸速度，其收發器功耗僅451.5 μW。 另一方面，為了方便使用者攜帶感測器，整合體積的微型化同為設計上的重要考量。本論文將使用嵌入式矽震盪器作為系統時脈產生器，以取代傳統使用的龐大石英晶體，達到全矽製程整合以實現微型化之目標，並也同時降低生產成本。由於矽震盪器之頻率精確度易受到製程、電壓和溫度飄移影響而受到限制，本論文提出對應的演算法和電路架構，用以補償和校正矽震盪器產生的大頻率誤差，提供無線傳輸所需的精確度。首先，針對基頻訊號的載波頻率偏差和時脈取樣偏移等效應，設計適當補償演算法以提升基頻處理器之頻率誤差容忍度(±500ppm)，增加與嵌入式矽震盪器整合之相容性。然而，過大的矽震盪器頻率誤差(±0.5~3%)，造成射頻訊號在接收器經混頻器降頻後，大部分基頻訊號已被移出濾波器頻帶之外，無法為基頻同步電路所偵測。因此，本論文更進一步提出頻率追蹤迴路，藉由追蹤無線射頻參考源校正系統頻率，使後端基頻電路得以進行資料解調。此頻率追蹤迴路操作於中頻帶，以全數位方式實現且不需改變前端電路架構，降低收斂過程中額外的功率消耗(15.2μW)。由晶片實作與量測結果，其收斂演算法可確保穩定且精確的收斂頻率(< ±100ppm)，充分相容於收發器之目標傳輸速率。嵌入式矽震盪器在運作時的功耗僅為7.6/20.2μW (5/20MHz)，由於震盪器為持續運作的元件，相較於石英晶體更能有效地降低系統總能量消耗。 為了使處理器操作在更低的工作電壓以節省功耗，同時讓感測器能搭配受輸出功率或電壓限制之輕薄電池元件，本論文更進一步討論低電壓低功耗元件庫之設計。考慮標準元件庫中低電壓運作的瓶頸為複雜度較高的正反器時序電路，本論文提出一基於脈衝觸發式栓鎖器架構之低功耗正反器。此正反器以較少的充放電節點完成資料栓鎖，相較於傳統脈衝觸發式栓鎖器減少65.8%的動態功率消耗；而其內部節點皆為靜態節點，且讀寫過程中無電流衝突行為，故適合在低電壓的環境下運作。此外，藉由脈衝觸發之特性，可有效降低近身網路系統中，因較長邏輯運算路徑於正反器資料端產生之暫態突波所耗費的功率。本論文使用此架構實現元件庫所需的正反器功能元件，包含同步、非同步和控制邏輯，並搭配計算機輔助設計軟體建構元件庫時序資訊。對比於晶圓廠所提供之標準元件庫(採用主流的低功耗主從式正反器架構)，本元件庫可節省47.1%的動態功率和29.8%的漏電流。利用此元件庫搭配全數位設計流程實現之基頻處理器，可操作在0.35伏特。對比於操作於0.5伏特的結果，節省了48.9%的總功率消耗；而相較於使用標準元件庫實現之結果，則降低了28.1%的總動態功率和10.1%的總漏電流。

Wireless body area network (WBAN) is an emerging technology which is specifically designed for body signal collection and monitoring to provide reliable physical information. Recently, WBAN is widely adopted to provide the ubiquitous healthcare applications or even multimedia information transmission, improving the service quality and scopes around human beings. In order to achieve long duration operation time for body signals, the WBAN system is required to provide reliable signal transmission, ultra-low power operation, and highly integrated tiny area for comfortable purposes. Considering several existed short-range transmission standards or techniques are unable to operate more than one week due to higher power cost. In addition, they mostly apply simple modulation scheme and thus cannot provide reliable body signal transmission. Accordingly, based on the analysis of WBAN operation behavior, this dissertation applies the orthogonal frequency division multiplexing (OFDM) modulation scheme to achieve reliable transmission link and high data rate (Mbps-scale) operation at the same time. The on-off duty-cycling transmission strategy is adopted for energy saving purpose. The system operates in sleep mode for most of time, and is only activated for burst data transmission. This behavior minimizes system duty cycle and saves considerable energy from transceiver circuits, resulting in longer operation duration. In circuit implementation, multiple supply voltage with power gating technique is considered to achieve the tradeoff between operation voltage and system duty cycle for energy optimization. The proposed baseband processer is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5V, the test chip is able to provide maximum date rate of 9.7 Mbps with modulator power consumption of 451.5 μW. On the other hand, the miniature integration form factor is also a crucial design issue for comfortable wearing and portability. Therefore, our design target is to integrate the on-chip CMOS oscillator into WBAN system to replace conventional bulky quartz crystal, resulting in miniature crystal-less design with less production cost. Since the frequency accuracy of CMOS oscillator is quite sensitive to process, voltage and temperature variations, this dissertation proposes the dedicated algorithm and system architecture to compensate large frequency error. Firstly, the baseband synchronizer is designed to extend system frequency error tolerance (±500ppm). However, the large frequency error (±0.5%~3%) caused by CMOS oscillator cannot be entirely compensated by baseband synchronizer because most of the received baseband signals are influenced by the large carrier frequency offset (CFO) and shifted to outside the low pass filter after down-conversion. Hence, a frequency tracking loop (FTL), operating at intermediate frequency (IF) band, is further proposed to perform system clock calibration by tracking a remote wireless RF reference. The FTL operation ensures the robust and accurate clock to enable correct and high data rate wireless link in crystal-less. According to chip experimental results, the FTL extends system frequency error tolerance to ±3%, where the convergence clock achieves the accuracy within ±100ppm. In addition, the CMOS oscillator consumes only 7.6/20.2μW in 5/20MHz, saving the always-on clock energy compared with using quartz crystal. To further reduce system power and scale operation voltage, this dissertation investigates the design of the low voltage and low power cell library. Considering the sequential flip flop (FF) circuit remains the bottleneck in voltage scaling due to its higher complexity than other Boolean logics, a 22T conditional supply coupling (CSC) pulsed-latch (PL) is proposed. CSC-PL completes storage function with minimal switching nodes, saving 65.8% active power compared with conventional implicit PL FFs. All internal nodes are designed in static without current contention, ensuring reliable driving ability for voltage scaling. Besides, its pulse triggered property effectively reduces the redundant glitch power caused by input transitions from longer computation logics in pipeline sages. Consequently, the required functional FF cells for processor designs are implemented in library, where the cell timings are characterized by EDA tool for cell-based design flow. Comparing with the foundry provided standard cells using power-efficient master-slave structure, the proposed cells reduce 47.1% active power and 29.8% idle leakage. With the proposed library, a baseband processor is fabricated in 90nm CMOS process and is able to operate at 0.35V, saving 48.9% total power compared with the case in 0.5V. The reduction of total active power and leakage are 28.1% and 10.1%, respectively, compared with the design using foundry standard cells.