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dc.contributor.authorLi, Yimingen_US
dc.contributor.authorYu, Shao-Mingen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.date.accessioned2014-12-08T15:05:34Z-
dc.date.available2014-12-08T15:05:34Z-
dc.date.issued2007-09-01en_US
dc.identifier.issn0167-9317en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.mee.2007.04.059en_US
dc.identifier.urihttp://hdl.handle.net/11536/4107-
dc.description.abstractIn this paper, we investigate the threshold voltage fluctuation for nanoscale metal-oxide-semiconductor field effect transistor (MOSFET) and silicon-on-insulator (SOI) devices. The threshold voltage fluctuation comes from random dopant and short channel effects. The ran dom-dopant- induced fluctuation is due to the random nature of ion implantation. The gatelength deviation and the line-edge roughness are mainly resulted from the short-channel effect. For the SOI devices, we should also consider the body thickness variation. In our investigation, the metal gate with high-K material MOSFET is a good choice to reduce fluctuation of threshold voltage when comparing to the poly gate MOSFET and thin-body SOI devices.en_US
dc.language.isoen_USen_US
dc.subjectthreshold voltage fluctuationen_US
dc.subjectrandom dopanten_US
dc.subjectprocess-variationen_US
dc.subjectgate-length deviationen_US
dc.subjectline-edge roughnessen_US
dc.subjectmodeling and simulationen_US
dc.titleProcess-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale CMOS and SOI devicesen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1016/j.mee.2007.04.059en_US
dc.identifier.journalMICROELECTRONIC ENGINEERINGen_US
dc.citation.volume84en_US
dc.citation.issue9-10en_US
dc.citation.spage2117en_US
dc.citation.epage2120en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000247378600065-
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