一個具備數位背景校正技術使用開迴路式殘值放大器之導管式類比數位轉換器

Abstract

如何設計一個具備高效能且高良率的類比數位轉換器一直是重要的研究課題，而在數位電路直接受惠於製程演進的利基下，利用數位校正機制使類比數位轉換器可達到操作在高速、高解析度且具有低功率消耗的特性，更是當下時勢之所趨。 有鑑於此，本論文提出一個可精確估測殘值放大器線性與三階非線性增益誤差的設計，透過全數位背景式的校正機制應用在導管式類比數位轉換器上，可有效大幅改善其電路效能，我們並以台積電 0.18um Mixed-Mode RF CMOS製程實現一個數位背景校正每秒一億次取樣十二位元使用開迴路式殘值放大器設計之導管式類比數位轉換器，電路架構共分三級：前二級校正級為(3+1)-bit，每校正級中殘值放大器之理想增益為8且其Multiplying DAC（MDAC）皆以開迴路式架構實現，因製程所產生之線性與非線性增益誤差則藉由可精確估測殘值放大器線性與三階非線性增益誤差的方法，再透過數位電路將誤差補償校正；而第三級為一個6-bit flash ADC。 當二級校正級均導入10%的線性和三階非線性增益誤差時，模擬結果顯示靜態參數校正前為DNL=0.5/-1.0LSB、INL=16.7/-16.7LSB，而校正後可提升至DNL=0.8/-1.0LSB、INL=0.6/-0.6LSB。動態參數方面在校正前SFDR=54.1dBc、SNR=46.2dB、SNDR=44.4dB、ENOB=7.1 bits，而校正後可大幅提升至SFDR=94.5dBc、SNR=71.0dB、SNDR=71.0dB、ENOB=11.5 bits 。在不包含全數位實現的Estimation和Calibration電路時此ADC功率消耗為71.2mW。 而晶片量測結果校正前ENOB=4.1 bits，校正後ENOB=5.3 bits，導致校正結果與模擬結果有差距的原因之一為模擬時未完整考量到當每一級解出的數位碼發生偏移誤差時，對後續估測和校正機制產生的影響。因為校正的演算法為一非線性函數，當含有偏移誤差之數位碼經過校正的演算法後，將影響到估測增益誤差的精確度，進而影響電路校正的結果。

The design of a high performance analog-to-digital converter (ADC) with a high yield is an important research issue. An interesting approach is designing the ADCs with the aid of some kinds of digital calibration schemes. Such an approach benefits from the low-power, high-resolution, high-speed, and portability features of digital circuits, while the analog design can be much simplified by using the simplest circuits to achieve low-power, high-resolution, and high-speed as well. This thesis proposes a digital background calibration design that can accurately estimate and calibrate the linear and the 3rd-order non-linear gain errors of the residue amplifiers in the pipelined ADC. The proposed 12-bit 100MS/s digitally background calibrated pipelined ADC using open-loop residue amplifiers was realized in TSMC 0.18μm Mixed-Mode RF CMOS technology. The pipelined ADC consists of cascaded three stages. The former two are the stages under calibration. Each of them has (3+1)-bit resolution and the nominal gains of the residue amplifiers in them are all eight. The final stage is a 6-bit flash ADC. The multiplying DACs in the stages under calibration are implemented using open-loop topology. By employing an estimation method that can accurately estimate the linear and the 3rd-order non-linear gain errors of the residue amplifiers and compensating these errors in the digital domain, the pipelined ADC can be calibrated to achieve a high SNDR even though the practical residue amplifiers have severe linear and non-linear gain errors due to fabrication variations. We added 10% linear and 10% the 3rd-order non-linear gain errors to the residue amplifiers in the stages under calibration to verify the effectiveness of the calibration scheme. The simulation results show that, the DNL and the INL of the ADC without calibration are within 0.5/-1.0 LSB and 16.7/-16.7 LSB, respectively and the SFDR=54.1dBc, SNR=46.2dB, SNDR=44.4dB, ENOB=7.1 bits. After activating the calibration, the DNL and the INL of the ADC are improved to be within 0.8/-1.0 LSB and 0.6/-0.6 LSB, respectively and the SFDR=94.5dBc, SNR=71.0dB, SNDR=71.0dB, ENOB=11.5 bits. All the simulation results show that the proposed digital background calibration design can significantly improve the ADC’s performances. Furthermore, the power consumption of the ADC is 71.2mW excluding the estimation and calibration circuits. The measurement results of the proposed 12-bit 100MS/s digitally background calibrated pipelined ADC show that the ENOB of the ADC with and without calibration are 5.3 bits and 4.1 bits, respectively. The ENOB is improved by 1.2 bits after activating the calibration. The improvement is not as much as what the simulations show. The main reason is that the calibration function used in this design is not linear. If the backend ADC has some offset, then the calibration function can not provide accurate data for the estimation block to estimate the gain errors of the residue amplifiers. It is our future work to address this issue.