具有新穎結構非揮發性記憶體

Abstract

隨著製程技術的快速演進，非揮發性記憶體的應用越來越廣泛如:隨身聽、筆記型電腦、I-phone、I-Pad…等等，因此高密度的非揮發性記憶體被強烈的需求，但是在傳統浮動閘極非揮發性記憶體微縮的上，遇到許多無法解決的問題如:穿隧氧化層的微縮與閘極長度的微縮，因此再穿隧氧化層微縮方面，SONOS-type與內嵌奈米元件記憶體被提出，而在閘極長度微縮方面，薄膜電晶體記憶體被廣泛的研究。 在本篇論文中，我們首先成功地利用非臨場(ex-situ)方法在氮化矽層內嵌矽奈米晶體(silicon nanocrystal)製造出新穎的SONOS型記憶體結構，並且可以達到多位元層級之操作。這個方法相當簡單和低成本。此次的實驗我們將聚焦於非臨場方法以不同時間堆疊矽奈米晶體，矽奈米晶體和矽奈米晶體與氮化矽界面將會提供載子捕捉層多餘的缺陷能階(trapped state)，因此矽奈米晶體密度較高的元件，可得到較多的缺陷能階，因此得到較好的元件特性。同時我們利用深層能階暫態頻譜偵測(Deep-Level-Transient-Spectroscopy)技術分析矽奈米晶體元件與一般SONOS記憶體之差別，明顯的得到額外的缺陷能階。此非揮性記憶體(non-volatile memory)元件具有極佳的特性表現：較大的記憶體窗(memory window)、長時間的載子保存性(data retention)。本研究有助於了解不同堆疊時間對於記憶體元件電性及物性的影響。 然而非臨場方式在氮化矽層內嵌矽奈米晶體必須經過多次的低壓化學氣化沉積製程，導致量產速度下降。因此我們在此提出臨場方法在氮化矽層內嵌矽奈米晶體，我們成功的製作了氮化矽內嵌矽奈米SONOS元件記憶體，可達到多位元層級與雙位元(2-bit/cell)操作，並且對其做了詳細的探討與研究，此方法相對於非臨場方法更為簡單、更低成本與CMOS有更高的相容性。首先，聚焦於不同時間沉積矽奈米晶體的物理特性研究，發現其奈米晶體隨著沉積時間越長，矽奈米晶體顆粒越大，其密度卻是有最佳化時間，並發現矽奈米晶體大小約為7~12 nm，密度約為7~9 x 1011 cm-2。同時，SONOS內嵌矽奈米元件有相當優秀的電性特性表現：較大的記憶窗口(>5.5 V)、低寫入/抹除電壓、輕微的閘極干擾與汲級干擾、可忽略的2-bit效應、較快的寫入/抹除速度、良好的資料保存能力(>108 s 只有13%的電荷損失)和優良的可靠度特性(一萬次操作後依然擁有3-V的記憶窗口)。 而在單晶金氧半場效電晶體元件持續的微縮下，將會遇到無可避免的問題如:短通道效應、穿隧效應、臨界電壓下降效應與汲極導致位能障下降，因此在此提出一個新穎PN二極體薄膜電晶體非揮發記憶體元件，並且在氮化矽層內嵌矽奈米晶體，此元件擁有許多優點如:製程簡單、可以達到高密度記憶體與相容於3-D電路整合系統。此元件分別利用熱電子注入與熱電動注入，來達成寫入與抹除動作，同時此三端點PN二極體薄膜電晶體元件利用能帶穿隧電流作為感應電流，此電流值可達到10-7安培，足夠做為感應電流用。並且此元件擁有相當大的記憶窗口(>12 V)與良好的電荷保存能力(經過108 s只有12%的電荷損失)。因此此元件相當適合應用於系統整合於面板與3-D電路整合。 由於現今電子產品的縮小如:越薄、越短與越小的情況下，對於多功能系統整合於晶片的需求越來越強烈，要在同一製程中達到同時製作出邏輯元件與一次性寫入記憶體元件，並且不須額外的製程與光罩是相當困難達成的。在此論文中我們提出低溫多晶矽薄膜電晶體利用SPC與MILC的通道層，搭配高介電常數介電質做為閘極氧化層，來達到邏輯元件與一次性寫入記憶體元件之應用，並且在此論文中詳細的討論其電特性。在邏輯元件方面，對具高介電質氧化層之低溫多晶矽薄膜電晶體分別利用SPC與MILC技術形成通道，分別得到良好的電特性如：較低的臨界電壓(Vt) -1.248 V與-0.905 V、較陡峭的次臨界擺盪(S.S.) 0.15 V/decade and 0.105 V/decade與較高的驅動電流。同時在一次性寫入記憶體元件中，SPC與MILC形成之通道層也有優良的電特性表現如:較大的記憶窗口(□IGIDL ~ 2.8 order and ~ 3.5 order)與優良的電荷保存特性(再85 oC的烘烤104 s下，分別只有17%與15.7%的電荷損失)。在不需要額外的製程與光罩下，邏輯元件與一次寫入性記憶體元件在相同的製程即可達成，因此此元件相當適合應用於系統整合於面板與3-D電路整合元件。

Recently, the nonvolatile memories have been undergoing rapid development for MP3 audio player, personal notebook, I-phone, and I-pad. The high density memories have been aggressively demanded. However, the conventional floating-gate memories have met physical limit owing to the scaled down of the tunneling oxide thickness and channel length. Therefore, for the scaled down of the tunneling oxide thickness issue, the SONOS-type memory and MOS memory embedded nanocrystal have been proposed. For the scaled down of channel length issue, the thin film transistors memory have been widely studied to increased the density of the NVM. In this dissertation, first, SONOS-type capacitances with embedded silicon nanocrystals (Si-NCs) in silicon nitride using ex-situ method with multi-level operation have been successfully demonstrated. Different Si-NCs deposition times by ex-situ method were investigated. The process is simple and low cost. This implies that higher dot size and density will increase the number of trapping states which can be located in Si-NCs, or at the interface of the silicon nitride and the Si-NCs. At the same time, the embedded silicon nanocrystals in silicon nitride for SONOS-type capacitances use the Deep-Level-Transient-Spectroscopy (DLTS) to analyze the extra trapped states. SONOS-type capacitances with embedded Si-NCs exhibit a significantly improved performance with a large memory window, low operating voltage and good retention time. However, the embedded silicon nanocrystal in silicon nitride using ex-situ method must has been multi-layers deposited by LPCVD system resulting in lower throughput. Therefore, the SONOS-type memory devices with embedded Si-NCs in silicon nitride using in-situ method with multi-level and 2-bit/cell operation have been successfully demonstrated and completely discussed. Compared with ex-situ Si-NCs method, the proposed in-situ Si-NCs deposition method exhibits the advantages of lower cost, simplicity and compatibility with modern IC processes. In the material analysis of silicon nitride embedded Si-NCs, a longer deposition time results in a larger Si-NCs size. However, the longest deposition time of Si-NCs does not show the highest density. Instead, the 60-sec deposition time shows the highest density among these samples. The mean size of Si-NCs and the aerial density turned out to be 7~12 nm and 7~9 x 1011 cm-2, respectively. The SONOS-type memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (>5.5-V), low operating voltage, greater tolerable gate and drain disturbance (Vt shift <0.2-V), negligible second-bit effect, high P/E speed, good retention time (>108s for 13% charge loss) and excellent endurance performance (after 10k P/E cycles memory window of 3-V). For the scaled down of the single crystal MOSFET, the many challenges, such as short channel effect, punch through effect, Vt roll-off and drain induced barrier lowing, can’t avoid. Therefore, a novel PN-diode (PND) structure of SONOS-type thin film transistor (TFT) non-volatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in silicon nitride layer using in-situ method is successfully demonstrated. This novel structure has many advantages, including a simple manufacturing process, high density, and suitability for three-dimensional (3-D) circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND TFT NVM is 10-7 A by band-to-band tunneling (BTBT) current. A much larger memory window (>12-V) and good data retention time (>108 sec for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel (SOP) and 3-D circuit integration. Recently, the electronic portable equipments have been scaled down, such as thin, short and small. The system of chip (SOC) has been aggressively demanded. However, the process is difficult to develop dual applications for logic device and one-time-programmable (OTP) memory, without extra process or extra mask. Therefore, SPC and MILC p-channel LTPS-TFTs with high-k dielectric for the dual applications of logic device and one-time-programmable memory have been successfully demonstrated and compared. For the logic device, the SPC- and MILC-TFT have the excellent electrical characteristics of low threshold voltage (Vth ~ -1.248 V and -0.905 V), steeper subthreshold swing (S.S ~ 0.15 V/decade and 0.105 V/decade) and higher driving current. For the OTP memory, the OTP memory with SPC and MILC channel films has excellent performance and good reliability under low operating voltage, a large memory window (□IGIDL ~ 2.8 order and ~ 3.5 order) and good data retention time (>104s at 85oC for ~ 17% and 15.7% charge loss). The logic device and one-time-programmable memory have been fabricated, simultaneously, without extra processes or extra mask. The devices fabricated in this work show strong potential for system-on-panel and 3-D integration applications.