完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, PR | en_US |
dc.date.accessioned | 2014-12-08T15:01:34Z | - |
dc.date.available | 2014-12-08T15:01:34Z | - |
dc.date.issued | 1997-08-01 | en_US |
dc.identifier.issn | 0020-7217 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/411 | - |
dc.description.abstract | A Hopfield-type neural network approach is presented, which leads to an analogue circuit for implementing the bit-level transform image. Unlike the conventional digital approach to image coding, the analogue coding system would operate at a much higher speed and it requires less hardware than a digital system. To utilize the concept of neural net, the computation of a two-dimensional DCT-based transform coding should be reformulated as minimizing a quadratic nonlinear programming problem subject to the corresponding 2s complement binary variables of two-dimensional DCT coefficients. A Hopfield-type neural net with a number of graded-response neurons designed to perform the quadractic nonlinear programming would lead to such a solution, in a time determined by RC time constants, not by algorithmic time complexity. Nevertheless, the existance of local minima in the energy function of the original Hopfield model implies that in general the correct globally optimal solution is not guaranteed. To tackle this difficulty, a network with an additional self-correction circuitry is developed to eliminate these local minima and yields the correct digital representations of 2-D DCT coefficients. A fourth-order Runge-Kutta simulation is conducted to verify the performance of the proposed analogue circuit. Experiments show that the circuit is quite robust and independent of parameter variations, and the computation time of an 8 x 8 DCT is estimated as 128 ns for RC = 10(-9). | en_US |
dc.language.iso | en_US | en_US |
dc.title | A self-correction Hopfield neural network for computing the bit-level transform image coding | en_US |
dc.type | Article | en_US |
dc.identifier.journal | INTERNATIONAL JOURNAL OF ELECTRONICS | en_US |
dc.citation.volume | 83 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 215 | en_US |
dc.citation.epage | 233 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.contributor.department | Institute of Communications Engineering | en_US |
顯示於類別: | 期刊論文 |